The SN74LS29x devices are programmable frequency dividers and digital timers contain 31 flip-flops plus 30 gates (in SN74LS292) or 15 flip-flops plus 29 gates (in SN74LS294) on a single chip. The count modulo is under digital control of the inputs provided. Both types feature an active-lowCLRclear input to initialize the state of all flip-flops. To facilitate the incoming inspection, test points are provided (TP1, TP2, and TP3 on the SN74LS292, and TP on the SN74LS294). These test points are not intended to drive system loads. Both types feature two clock inputs; either one may be used for clock gating. A brief look at the digital timing capabilities of the SN74LS292 shows that with a 1-MHz input frequency, programming for 210gives a period of 1.024 ms, 220gives a period of 1.05 sec, 226gives a period of 1.12 min, and 231gives a period of 35.79 min. These devices are easily cascadable, giving limitless possibilities to achievable timing delays. The SN74LS29x devices are programmable frequency dividers and digital timers contain 31 flip-flops plus 30 gates (in SN74LS292) or 15 flip-flops plus 29 gates (in SN74LS294) on a single chip. The count modulo is under digital control of the inputs provided. Both types feature an active-lowCLRclear input to initialize the state of all flip-flops. To facilitate the incoming inspection, test points are provided (TP1, TP2, and TP3 on the SN74LS292, and TP on the SN74LS294). These test points are not intended to drive system loads. Both types feature two clock inputs; either one may be used for clock gating. A brief look at the digital timing capabilities of the SN74LS292 shows that with a 1-MHz input frequency, programming for 210gives a period of 1.024 ms, 220gives a period of 1.05 sec, 226gives a period of 1.12 min, and 231gives a period of 35.79 min. These devices are easily cascadable, giving limitless possibilities to achievable timing delays.