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74AC563 Series

Octal D-Type Transparent Latches With 3-State Outputs

Manufacturer: Texas Instruments

Catalog(8 parts)

PartMounting TypePackage / Case▲▼Package / Case▲▼Package / CaseCurrent - Output High, Low▲▼Current - Output High, Low▲▼Independent Circuits▲▼Supplier Device PackageCircuitDelay Time - Propagation▲▼Output TypeOperating Temperature▲▼Operating Temperature▲▼Logic TypeVoltage - Supply▲▼Voltage - Supply▲▼Package / Case▲▼
Texas Instruments
SN74AC563PW
D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-TSSOP
Surface Mount
0.004394200164824724 m
0.004399999976158142 m
20-TSSOP
0.024000000208616257 A
0.024000000208616257 A
1 ul
20-TSSOP
8:8
4.599999936516497e-9 s
Tri-State
-40 °C
85 °C
D-Type Transparent Latch
2 V
6 V
Texas Instruments
SN74AC563DW
D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-SOIC
Surface Mount
0.007493000011891127 m, 0.007499999832361937 m
20-SOIC
0.024000000208616257 A
0.024000000208616257 A
1 ul
20-SOIC
8:8
4.599999936516497e-9 s
Tri-State
-40 °C
85 °C
D-Type Transparent Latch
2 V
6 V
Texas Instruments
SN74AC563N
D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-PDIP
Through Hole
0.007619999814778566 m
20-DIP
0.024000000208616257 A
0.024000000208616257 A
1 ul
20-PDIP
8:8
4.599999936516497e-9 s
Tri-State
-40 °C
85 °C
D-Type Transparent Latch
2 V
6 V
0.007619999814778566 m
Texas Instruments
SN74AC563DWR
D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-SOIC
Surface Mount
0.007493000011891127 m, 0.007499999832361937 m
20-SOIC
0.024000000208616257 A
0.024000000208616257 A
1 ul
20-SOIC
8:8
4.599999936516497e-9 s
Tri-State
-40 °C
85 °C
D-Type Transparent Latch
2 V
6 V
Texas Instruments
SN74AC563PWR
D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-TSSOP
Surface Mount
0.004394200164824724 m
0.004399999976158142 m
20-TSSOP
0.024000000208616257 A
0.024000000208616257 A
1 ul
20-TSSOP
8:8
4.599999936516497e-9 s
Tri-State
-40 °C
85 °C
D-Type Transparent Latch
2 V
6 V
Texas Instruments
CD74AC563EG4
D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-PDIP
Through Hole
0.007619999814778566 m
20-DIP
0.024000000208616257 A
0.024000000208616257 A
1 ul
20-PDIP
8:8
3.000000026176508e-9 s
Tri-State
-55 °C
125 °C
D-Type Transparent Latch
1.5 V
5.5 V
0.007619999814778566 m
Texas Instruments
CD74AC563E
D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-PDIP
Through Hole
0.007619999814778566 m
20-DIP
0.024000000208616257 A
0.024000000208616257 A
1 ul
20-PDIP
8:8
3.000000026176508e-9 s
Tri-State
-55 °C
125 °C
D-Type Transparent Latch
1.5 V
5.5 V
0.007619999814778566 m
Texas Instruments
SN74AC563PWLE
D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-TSSOP
Surface Mount
0.004394200164824724 m
0.004399999976158142 m
20-TSSOP
0.024000000208616257 A
0.024000000208616257 A
1 ul
20-TSSOP
8:8
4.599999936516497e-9 s
Tri-State
-40 °C
85 °C
D-Type Transparent Latch
2 V
6 V

Key Features

• 2-V to 6-V VCCOperationInputs Accept Voltages to 6 VMax tpdof 9 ns at 5 V3-State Inverting Outputs Drive Bus Lines DirectlyFull Parallel Access for LoadingFlow-Through Architecture to Optimize PCB Layout2-V to 6-V VCCOperationInputs Accept Voltages to 6 VMax tpdof 9 ns at 5 V3-State Inverting Outputs Drive Bus Lines DirectlyFull Parallel Access for LoadingFlow-Through Architecture to Optimize PCB Layout

Description

AI
The ’AC563 devices are octal D-type transparent latches with 3-state outputs. When the latch-enable (LE) input is high, the Q\ outputs follow the complements of the data (D) inputs. When LE is taken low, the Q\ outputs are latched at the inverse logic levels set up at the D inputs. A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. (OE)\ does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The ’AC563 devices are octal D-type transparent latches with 3-state outputs. When the latch-enable (LE) input is high, the Q\ outputs follow the complements of the data (D) inputs. When LE is taken low, the Q\ outputs are latched at the inverse logic levels set up at the D inputs. A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. (OE)\ does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.