74LV74 Series

Enhanced Product Dual Positive-Edge-Triggered D-Type Flip-Flops

Catalog(7 parts)

Part	Package / Case▲▼	Package / Case▲▼	Package / Case	Current - Quiescent (Iq)▲▼	Function	Trigger Type	Output Type	Current - Output High, Low▲▼	Current - Output High, Low▲▼	Clock Frequency▲▼	Operating Temperature▲▼	Operating Temperature▲▼	Number of Elements▲▼	Input Capacitance▲▼	Voltage - Supply▲▼	Voltage - Supply▲▼	Mounting Type	Max Propagation Delay @ V, Max CL▲▼	Number of Bits per Element▲▼	Type	Package / Case▲▼	Package / Case▲▼	Supplier Device Package	Grade	Qualification
Texas Instruments SN74LV74ADR Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-SOIC (0.154", 3.90mm Width)	0.003899999894201755 m	0.003911599982529879 m	14-SOIC	0.000019999999494757503 A	Reset, Set(Preset)	Positive Edge	Complementary	0.012000000104308128 A	0.012000000104308128 A	140000000 Hz	-40 °C	125 °C	2 ul	1.9999999920083944e-12 F	2 V	5.5 V	Surface Mount	9.29999988130703e-9 s	1 ul	D-Type
Texas Instruments SN74LV74AD Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-SOIC (0.154", 3.90mm Width)	0.003899999894201755 m	0.003911599982529879 m	14-SOIC	0.000019999999494757503 A	Reset, Set(Preset)	Positive Edge	Complementary	0.012000000104308128 A	0.012000000104308128 A	140000000 Hz	-40 °C	125 °C	2 ul	1.9999999920083944e-12 F	2 V	5.5 V	Surface Mount	9.29999988130703e-9 s	1 ul	D-Type
Texas Instruments SN74LV74APWRE4 Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-TSSOP (0.173", 4.40mm Width)			14-TSSOP	0.000019999999494757503 A	Reset, Set(Preset)	Positive Edge	Complementary	0.012000000104308128 A	0.012000000104308128 A	140000000 Hz	-40 °C	125 °C	2 ul	1.9999999920083944e-12 F	2 V	5.5 V	Surface Mount	9.29999988130703e-9 s	1 ul	D-Type	0.004394200164824724 m	0.004399999976158142 m	14-TSSOP
Texas Instruments SN74LV74APWT Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-TSSOP (0.173", 4.40mm Width)			14-TSSOP	0.000019999999494757503 A	Reset, Set(Preset)	Positive Edge	Complementary	0.012000000104308128 A	0.012000000104308128 A	140000000 Hz	-40 °C	125 °C	2 ul	1.9999999920083944e-12 F	2 V	5.5 V	Surface Mount	9.29999988130703e-9 s	1 ul	D-Type	0.004394200164824724 m	0.004399999976158142 m	14-TSSOP
Texas Instruments SN74LV74ARGYR Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-VFQFN Exposed Pad			14-VFQFN Exposed Pad	0.000019999999494757503 A	Reset, Set(Preset)	Positive Edge	Complementary	0.012000000104308128 A	0.012000000104308128 A	140000000 Hz	-40 °C	125 °C	2 ul	1.9999999920083944e-12 F	2 V	5.5 V	Surface Mount	9.29999988130703e-9 s	1 ul	D-Type			14-VQFN (3.5x3.5)
Texas Instruments SN74LV74AQDRQ1 Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-SOIC (0.154", 3.90mm Width)	0.003899999894201755 m	0.003911599982529879 m	14-SOIC	0.000019999999494757503 A	Reset, Set(Preset)	Positive Edge	Complementary	0.012000000104308128 A	0.012000000104308128 A	140000000 Hz	-40 °C	125 °C	2 ul	1.9999999920083944e-12 F	2 V	5.5 V	Surface Mount	9.29999988130703e-9 s	1 ul	D-Type				Automotive	AEC-Q100
Texas Instruments SN74LV74AQPWRG4Q1 Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-TSSOP (0.173", 4.40mm Width)			14-TSSOP	0.000019999999494757503 A	Reset, Set(Preset)	Positive Edge	Complementary	0.012000000104308128 A	0.012000000104308128 A	140000000 Hz	-40 °C	125 °C	2 ul	1.9999999920083944e-12 F	2 V	5.5 V	Surface Mount	9.29999988130703e-9 s	1 ul	D-Type	0.004394200164824724 m	0.004399999976158142 m	14-TSSOP	Automotive	AEC-Q100

Key Features

• Controlled BaselineOne Assembly/Test Site, One Fabrication SiteExtended Temperature Performance of -55°C to 125°CEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product-Change NotificationQualification Pedigree(1)2-V to 5.5-V VCCOperationMax tpdof 13 ns at 5 VTypical VOLP(Output Ground Bounce) <0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot) >2.3 V at VCC= 3.3 V, TA= 25°CSupports Mixed-Mode Voltage Operation on All PortsIoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.Controlled BaselineOne Assembly/Test Site, One Fabrication SiteExtended Temperature Performance of -55°C to 125°CEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product-Change NotificationQualification Pedigree(1)2-V to 5.5-V VCCOperationMax tpdof 13 ns at 5 VTypical VOLP(Output Ground Bounce) <0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot) >2.3 V at VCC= 3.3 V, TA= 25°CSupports Mixed-Mode Voltage Operation on All PortsIoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

Description

These dual positive-edge-triggered D-type flip-flops are designed for 2-V to 5.5-V VCCoperation. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. These dual positive-edge-triggered D-type flip-flops are designed for 2-V to 5.5-V VCCoperation. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.