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74AHCT74 Series

Enhanced Product Dual Positive-Edge-Triggered D-Type Flip-Flop With Clear And Preset

Manufacturer: Texas Instruments

Catalog(12 parts)

PartVoltage - SupplyVoltage - SupplyMounting TypeMax Propagation Delay @ V, Max CLClock FrequencyNumber of ElementsCurrent - Output High, LowCurrent - Output High, LowOperating TemperatureOperating TemperatureTrigger TypeTypeSupplier Device PackagePackage / CasePackage / CasePackage / CaseCurrent - Quiescent (Iq)Input CapacitanceOutput TypeNumber of Bits per ElementFunctionPackage / CasePackage / CaseQualificationGradePackage / Case
Texas Instruments
SN74AHCT74PWG4
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-TSSOP (0.173", 4.40mm Width)
5.5 V
4.5 V
Surface Mount
8.799999839936845e-9 s
140000000 Hz
2 ul
0.00800000037997961 A
0.00800000037997961 A
-40 °C
125 °C
Positive Edge
D-Type
14-TSSOP
14-TSSOP
0.004394200164824724 m
0.004399999976158142 m
0.0000019999999949504854 A
1.9999999920083944e-12 F
Complementary
1 ul
Reset, Set(Preset)
Texas Instruments
SN74AHCT74RGYR
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-VFQFN Exposed Pad
5.5 V
4.5 V
Surface Mount
8.799999839936845e-9 s
140000000 Hz
2 ul
0.00800000037997961 A
0.00800000037997961 A
-40 °C
125 °C
Positive Edge
D-Type
14-VQFN (3.5x3.5)
14-VFQFN Exposed Pad
0.0000019999999949504854 A
1.9999999920083944e-12 F
Complementary
1 ul
Reset, Set(Preset)
Texas Instruments
SN74AHCT74MPWREP
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-TSSOP (0.173", 4.40mm Width)
5.5 V
4.5 V
Surface Mount
8.799999839936845e-9 s
140000000 Hz
2 ul
0.00800000037997961 A
0.00800000037997961 A
-55 °C
125 °C
Positive Edge
D-Type
14-TSSOP
14-TSSOP
0.004394200164824724 m
0.004399999976158142 m
0.0000019999999949504854 A
1.9999999920083944e-12 F
Complementary
1 ul
Reset, Set(Preset)
Texas Instruments
SN74AHCT74DR
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-SOIC (0.154", 3.90mm Width)
5.5 V
4.5 V
Surface Mount
8.799999839936845e-9 s
140000000 Hz
2 ul
0.00800000037997961 A
0.00800000037997961 A
-40 °C
125 °C
Positive Edge
D-Type
14-SOIC
0.0000019999999949504854 A
1.9999999920083944e-12 F
Complementary
1 ul
Reset, Set(Preset)
0.003899999894201755 m
0.003911599982529879 m
Texas Instruments
SN74AHCT74MDREP
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-SOIC (0.154", 3.90mm Width)
5.5 V
4.5 V
Surface Mount
8.799999839936845e-9 s
140000000 Hz
2 ul
0.00800000037997961 A
0.00800000037997961 A
-55 °C
125 °C
Positive Edge
D-Type
14-SOIC
0.0000019999999949504854 A
1.9999999920083944e-12 F
Complementary
1 ul
Reset, Set(Preset)
0.003899999894201755 m
0.003911599982529879 m
Texas Instruments
SN74AHCT74QDRG4Q1
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-SOIC (0.154", 3.90mm Width)
5.5 V
4.5 V
Surface Mount
8.799999839936845e-9 s
140000000 Hz
2 ul
0.00800000037997961 A
0.00800000037997961 A
-40 °C
125 °C
Positive Edge
D-Type
14-SOIC
0.0000019999999949504854 A
1.9999999920083944e-12 F
Complementary
1 ul
Reset, Set(Preset)
0.003899999894201755 m
0.003911599982529879 m
AEC-Q100
Automotive
Texas Instruments
SN74AHCT74PW
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-TSSOP (0.173", 4.40mm Width)
5.5 V
4.5 V
Surface Mount
1.1400000055061811e-8 s
140000000 Hz
2 ul
0.00800000037997961 A
0.00800000037997961 A
-40 °C
125 °C
Positive Edge
D-Type
14-TSSOP
14-TSSOP
0.004394200164824724 m
0.004399999976158142 m
0.0000019999999949504854 A
1.9999999920083944e-12 F
Complementary
1 ul
Reset, Set(Preset)
Texas Instruments
SN74AHCT74DGVR
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-TFSOP (0.173", 4.40mm Width)
5.5 V
4.5 V
Surface Mount
8.799999839936845e-9 s
140000000 Hz
2 ul
0.00800000037997961 A
0.00800000037997961 A
-40 °C
125 °C
Positive Edge
D-Type
14-TFSOP
0.0000019999999949504854 A
1.9999999920083944e-12 F
Complementary
1 ul
Reset, Set(Preset)
0.004399999976158142 m
Texas Instruments
SN74AHCT74PWRG4
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-TSSOP (0.173", 4.40mm Width)
5.5 V
4.5 V
Surface Mount
8.799999839936845e-9 s
140000000 Hz
2 ul
0.00800000037997961 A
0.00800000037997961 A
-40 °C
125 °C
Positive Edge
D-Type
14-TSSOP
14-TSSOP
0.004394200164824724 m
0.004399999976158142 m
0.0000019999999949504854 A
1.9999999920083944e-12 F
Complementary
1 ul
Reset, Set(Preset)
Texas Instruments
SN74AHCT74DBR
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-SSOP (0.209", 5.30mm Width)
5.5 V
4.5 V
Surface Mount
8.799999839936845e-9 s
140000000 Hz
2 ul
0.00800000037997961 A
0.00800000037997961 A
-40 °C
125 °C
Positive Edge
D-Type
14-SSOP
14-SSOP
0.0000019999999949504854 A
1.9999999920083944e-12 F
Complementary
1 ul
Reset, Set(Preset)
0.0052999998442828655 m
0.005308600142598152 m
Texas Instruments
SN74AHCT74QPWRG4Q1
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-TSSOP (0.173", 4.40mm Width)
5.5 V
4.5 V
Surface Mount
8.799999839936845e-9 s
140000000 Hz
2 ul
0.00800000037997961 A
0.00800000037997961 A
-40 °C
125 °C
Positive Edge
D-Type
14-TSSOP
14-TSSOP
0.004394200164824724 m
0.004399999976158142 m
0.0000019999999949504854 A
1.9999999920083944e-12 F
Complementary
1 ul
Reset, Set(Preset)
AEC-Q100
Automotive
Texas Instruments
SN74AHCT74N
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-DIP (0.300", 7.62mm)
5.5 V
4.5 V
Through Hole
8.799999839936845e-9 s
140000000 Hz
2 ul
0.00800000037997961 A
0.00800000037997961 A
-40 °C
125 °C
Positive Edge
D-Type
14-DIP
0.0000019999999949504854 A
1.9999999920083944e-12 F
Complementary
1 ul
Reset, Set(Preset)
0.007619999814778566 m
0.007619999814778566 m

Key Features

Controlled BaselineOne Assembly/Test Site, One Fabrication SiteExtended Temperature Performance of –55°C to 125°CEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product-Change NotificationQualification PedigreeInputs Are TTL-Voltage CompatibleEPIC™ (Enhanced-Performance Implanted CMOS) ProcessLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.EPIC is a trademark of Texas Instruments.Controlled BaselineOne Assembly/Test Site, One Fabrication SiteExtended Temperature Performance of –55°C to 125°CEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product-Change NotificationQualification PedigreeInputs Are TTL-Voltage CompatibleEPIC™ (Enhanced-Performance Implanted CMOS) ProcessLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.EPIC is a trademark of Texas Instruments.

Description

AI
The SN74AHCT74 is a dual positive-edge-triggered D-type flip-flop. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The SN74AHCT74 is a dual positive-edge-triggered D-type flip-flop. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.