SN74ABT125Q-Q1 Series

Automotive 4-ch, 4.5-V to 5.5-V buffers with TTL-compatible CMOS inputs and 3-state outputs

Catalog

Automotive 4-ch, 4.5-V to 5.5-V buffers with TTL-compatible CMOS inputs and 3-state outputs

Part	Operating Temperature [Min]	Operating Temperature [Max]	Grade	Mounting Type	Qualification	Logic Type	Package / Case [x]	Package / Case [y]	Package / Case	Number of Elements	Output Type	Number of Bits per Element	Voltage - Supply [Min]	Voltage - Supply [Max]	Current - Output High, Low
Texas Instruments SN74ABT125QDRQ1
Texas Instruments SN74ABT125QDRG4Q1
Texas Instruments SN74ABT125QDRQ1	-40 °C	125 °C	Automotive	Surface Mount	AEC-Q100	Buffer, Non-Inverting	0.154 in	3.9 mm	14-SOIC	4	3-State	1	4.5 V	5.5 V	16 mA, 32 mA
Texas Instruments SN74ABT125QDRG4Q1
Texas Instruments SN74ABT125QDRG4Q1	-40 °C	125 °C	Automotive	Surface Mount	AEC-Q100	Buffer, Non-Inverting	0.154 in	3.9 mm	14-SOIC	4	3-State	1	4.5 V	5.5 V	16 mA, 32 mA

Catalog

Automotive 4-ch, 4.5-V to 5.5-V buffers with TTL-compatible CMOS inputs and 3-state outputs

Key Features

• Qualified for Automotive ApplicationsTypical VOLP(Output Ground Bounce)<1 V at VCC= 5 V, TA= 25°CHigh-Drive Outputs(–16-mA IOH, 32-mA IOL)Ioffand Power-Up 3-State Support Hot InsertionLatch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)Qualified for Automotive ApplicationsTypical VOLP(Output Ground Bounce)<1 V at VCC= 5 V, TA= 25°CHigh-Drive Outputs(–16-mA IOH, 32-mA IOL)Ioffand Power-Up 3-State Support Hot InsertionLatch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)

Description

The SN74ABT125Q-Q1 quadruple bus buffer gate features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE)input is high. This device is fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74ABT125Q-Q1 quadruple bus buffer gate features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE)input is high. This device is fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.