CD74HC4017 Series
High Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
High Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs
Part | Voltage - Supply [Max] | Voltage - Supply [Min] | Direction | Operating Temperature [Min] | Operating Temperature [Max] | Supplier Device Package | Number of Elements [custom] | Reset | Timing | Trigger Type | Package / Case | Package / Case | Logic Type | Mounting Type | Count Rate | Number of Bits per Element | Package / Case [x] | Package / Case [x] |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD74HC4017MT | 6 V | 2 V | Up | -55 C | 125 °C | 16-SOIC | 1 | Asynchronous | Synchronous | Negative, Positive | 16-SOIC | 0.154 in, 3.9 mm Width | Counter, Decade | Surface Mount | 35 MHz | 10 | ||
Texas Instruments CD74HC4017E | 6 V | 2 V | Up | -55 C | 125 °C | 16-PDIP | 1 | Asynchronous | Synchronous | Negative, Positive | 16-DIP | 0.3 in, 7.62 mm | Counter, Decade | Through Hole | 35 MHz | 10 | ||
Texas Instruments CD74HC4017M | 6 V | 2 V | Up | -55 C | 125 °C | 16-SOIC | 1 | Asynchronous | Synchronous | Negative, Positive | 16-SOIC | 0.154 in, 3.9 mm Width | Counter, Decade | Surface Mount | 35 MHz | 10 | ||
Texas Instruments CD74HC4017NSR | 6 V | 2 V | Up | -55 C | 125 °C | 16-SO | 1 | Asynchronous | Synchronous | Negative, Positive | 16-SOIC (0.209", 5.30mm Width) | Counter, Decade | Surface Mount | 35 MHz | 10 | |||
Texas Instruments CD74HC4017M96 | 6 V | 2 V | Up | -55 C | 125 °C | 16-SOIC | 1 | Asynchronous | Synchronous | Negative, Positive | 16-SOIC | 0.154 in, 3.9 mm Width | Counter, Decade | Surface Mount | 35 MHz | 10 | ||
Texas Instruments CD74HC4017PWR | 6 V | 2 V | Up | -55 C | 125 °C | 16-TSSOP | 1 | Asynchronous | Synchronous | Negative, Positive | 16-TSSOP | Counter, Decade | Surface Mount | 35 MHz | 10 | 0.173 " | 4.4 mm |
Key Features
• Fully Static OperationBuffered InputsCommon ResetPositive Edge ClockingTypical fMAX= 50MHz at VCC=5V,CL= 15pF, TA=25°CFanout (Over Temperature Range)Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . -55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VFully Static OperationBuffered InputsCommon ResetPositive Edge ClockingTypical fMAX= 50MHz at VCC=5V,CL= 15pF, TA=25°CFanout (Over Temperature Range)Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . -55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5V
Description
AI
The ’HC4017 is a high speed silicon gate CMOS 5-stage Johnson counter with 10 decoded outputs. Each of the decoded outputs is normally low and sequentially goes high on the low to high transition clock period of the 10 clock period cycle. The CARRY (TC) output transitions low to high after OUTPUT 10 goes low, and can be used in conjunction with the CLOCK ENABLE (CE\) to cascade several stages. The CLOCK ENABLE input disables counting when in the high state. A RESET (MR) input is also provided which when taken high sets all the decoded outputs, except "0", low.
The device can drive up to 10 low power Schottky equivalent loads.
The ’HC4017 is a high speed silicon gate CMOS 5-stage Johnson counter with 10 decoded outputs. Each of the decoded outputs is normally low and sequentially goes high on the low to high transition clock period of the 10 clock period cycle. The CARRY (TC) output transitions low to high after OUTPUT 10 goes low, and can be used in conjunction with the CLOCK ENABLE (CE\) to cascade several stages. The CLOCK ENABLE input disables counting when in the high state. A RESET (MR) input is also provided which when taken high sets all the decoded outputs, except "0", low.
The device can drive up to 10 low power Schottky equivalent loads.