TPD4S1394 Series

The TPD4S1394 provides robust system level ESD solution for the IEEE 1394 port, along with a live insertion detection mechanism for high-speed lines interfacing a low-voltage, ESD sensitive core chipset. This device protects and monitors up to two differential input pairs. The optimized line capacitance protects the data lines with data rates in excess of 1.6 GHz without degrading signal integrity. The TPD4S1394 incorporates a live insertion detection circuit whose output state changes when improper voltage levels are present on the input data lines. The FWPWR_EN signal controls an external FireWire port power switch. During the live insertion event if there is a floating GND or a high level signal at the D+ or D– pins, the internal comparator detects the changes and pull the FWPWR_EN signal to a low state. When FWPWR_EN is driven low, there is an internal delay mechanism preventing it from being driven to the high state regardless of the inputs to the comparator. Additionally, the TPD4S1394 performs ESD protection on the four inputs pins: D1+, D1–, D2+, and D2–. The TPD4S1394 conforms to the IEC61000-4-2 (Level 4) ESD protection and ±15-kV HBM ESD protection. The TPD4S1394 is characterized for operation over ambient air temperature of –40°C to 85°C. A 0.1-µF decoupling capacitor is required at VCC. The TPD4S1394 provides robust system level ESD solution for the IEEE 1394 port, along with a live insertion detection mechanism for high-speed lines interfacing a low-voltage, ESD sensitive core chipset. This device protects and monitors up to two differential input pairs. The optimized line capacitance protects the data lines with data rates in excess of 1.6 GHz without degrading signal integrity. The TPD4S1394 incorporates a live insertion detection circuit whose output state changes when improper voltage levels are present on the input data lines. The FWPWR_EN signal controls an external FireWire port power switch. During the live insertion event if there is a floating GND or a high level signal at the D+ or D– pins, the internal comparator detects the changes and pull the FWPWR_EN signal to a low state. When FWPWR_EN is driven low, there is an internal delay mechanism preventing it from being driven to the high state regardless of the inputs to the comparator. Additionally, the TPD4S1394 performs ESD protection on the four inputs pins: D1+, D1–, D2+, and D2–. The TPD4S1394 conforms to the IEC61000-4-2 (Level 4) ESD protection and ±15-kV HBM ESD protection. The TPD4S1394 is characterized for operation over ambient air temperature of –40°C to 85°C. A 0.1-µF decoupling capacitor is required at VCC.