66AK2G12 Series
High performance multicore DSP+Arm - 1x Arm A15 cores, 1x C66x DSP core
Manufacturer: Texas Instruments
Catalog(7 parts)
| Part | Package / Case | Voltage - I/O▲▼ | Mounting Type | Operating Temperature▲▼ | Operating Temperature▲▼ | Non-Volatile Memory | Voltage - Core▲▼ | Type | Supplier Device Package | On-Chip RAM▲▼ | Interface | Clock Rate▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments 66AK2G12ABYA100E | 625-LFBGA, FCBGA | 1.7999999523162842 V, 3.299999952316284 V | Surface Mount | -40 °C | 105 °C | External | 1 V | DSP+ARM® | 625-FCBGA (21x21) | 8388608 b | CAN, DMA, EBI/EMI, Ethernet, I2C, McASP, McBSP, MMC/SD, QSPI, SPI, UART, USB | |
Texas Instruments 66AK2G12ABYA60ES | 625-LFBGA, FCBGA | 1.7999999523162842 V, 3.299999952316284 V | Surface Mount | -40 °C | 105 °C | External | 0.8999999761581421 V | DSP+ARM® | 625-FCBGA (21x21) | 8388608 b | CAN, DMA, EBI/EMI, Ethernet, I2C, McASP, McBSP, MMC/SD, QSPI, SPI, UART, USB | 600000000 Hz |
Texas Instruments 66AK2G12ABYT100 | 625-LFBGA, FCBGA | 1.7999999523162842 V, 3.299999952316284 V | Surface Mount | -40 °C | 125 °C | External | 1 V | DSP+ARM® | 625-FCBGA (21x21) | 8388608 b | CAN, DMA, EBI/EMI, Ethernet, I2C, McASP, McBSP, MMC/SD, QSPI, SPI, UART, USB | |
Texas Instruments 66AK2G12ABYA60 | 625-LFBGA, FCBGA | 1.7999999523162842 V, 3.299999952316284 V | Surface Mount | -40 °C | 105 °C | External | 0.8999999761581421 V | DSP+ARM® | 625-FCBGA (21x21) | 8388608 b | CAN, DMA, EBI/EMI, Ethernet, I2C, McASP, McBSP, MMC/SD, QSPI, SPI, UART, USB | 600000000 Hz |
Texas Instruments 66AK2G12ABY100 | 625-LFBGA, FCBGA | 1.7999999523162842 V, 3.299999952316284 V | Surface Mount | 0 °C | 90 °C | External | 1 V | DSP+ARM® | 625-FCBGA (21x21) | 8388608 b | CAN, DMA, EBI/EMI, Ethernet, I2C, McASP, McBSP, MMC/SD, QSPI, SPI, UART, USB | |
Texas Instruments 66AK2G12ABYA100 | 625-LFBGA, FCBGA | 1.7999999523162842 V, 3.299999952316284 V | Surface Mount | -40 °C | 105 °C | External | 1 V | DSP+ARM® | 625-FCBGA (21x21) | 8388608 b | CAN, DMA, EBI/EMI, Ethernet, I2C, McASP, McBSP, MMC/SD, QSPI, SPI, UART, USB | |
Texas Instruments 66AK2G12ABYA60E | 625-LFBGA, FCBGA | 1.7999999523162842 V, 3.299999952316284 V | Surface Mount | -40 °C | 105 °C | External | 0.8999999761581421 V | DSP+ARM® | 625-FCBGA (21x21) | 8388608 b | CAN, DMA, EBI/EMI, Ethernet, I2C, McASP, McBSP, MMC/SD, QSPI, SPI, UART, USB | 600000000 Hz |
Key Features
• Processor cores:Arm®Cortex®-A15 microprocessor unit (Arm A15) subsystem at up to 1000 MHzSupports full Implementation of Armv7-A architecture instruction setIntegrated SIMDv2 (Arm®Neon™ Technology) and VFPv4 (Vector Floating Point)32KB of L1 program memory32KB of L1 data memory512KB of L2 memoryError Correction Code (ECC) protection for L1 data memory ECC for L2 memoryParity protection for L1 program memoryGlobal Timebase Counter (GTC)64-Bit free-running counter that provides timebase for Arm A15 internal timersCompliant to Armv7 MPCore Architecture for Generic TimersC66x fixed- and floating-point VLIW DSP subsystem at up to 1000 MHzFully object-code compatible With C67x+ and C64x+ cores32KB of L1 program memory32KB of L1 data memory1024KB of L2 configurable as L2 RAM or cacheError detection for L1 program memoryECC for L1 data memoryECC for L2 data memoryIndustrial subsystem:Up to Two Programmable Real-Time Unit and Industrial Communication Subsystems (PRU-ICSS), each supports:Two Programmable Real-Time Units (PRUs) with enhanced multiplier and accumulator, each PRU supports:16KB of program memory With ECC8KB of data memory With ECCCRC32 and CRC16 hardware accelerator20 × enhanced GPIOSerial Capture Unit (SCU), supporting direct connection, 16-bit parallel capture, 28-bit shift, MII_RT, EnDat 2.2 protocol and Sigma-Delta demodulationScratch pad and XFR direct connect64KB of general-purpose memory With ECCOne Ethernet MII_RT module with two MII ports configurable for connection with each PRU; supports multiple industrial communication protocolsIndustrial Ethernet Peripheral (IEP) to manage and generate industrial Ethernet functionsBuilt-In Universal Asynchronous Receiver and Transmitter (UART) 16550, with a dedicated 192-MHz clock to support 12-Mbps PROFIBUS®Built-In industrial Ethernet 64-Bit timerBuilt-In enhanced capture module (eCAP)Memory subsystem:Multicore Shared Memory Controller (MSMC) with 1024KB of shared L2 RAMProvides high-performance interconnect to internal shared SRAM and DDR EMIF for both Arm A15 and C66x AccessSupports Arm I/O coherency where Arm A15 is cache coherent to other system masters accessing the MSMC-SRAM or DDR EMIFSupports ECC on SRAMUp to 36-Bit DDR External Memory Interface (EMIF)Supports DDR3L at up to 1066 MT/sSupports 4-GB memory address rangeSupports 32-Bit SDRAM data bus with 4-bit ECCSupports 16-Bit and 32-Bit SDRAM data bus without ECCGeneral-Purpose Memory Controller (GPMC)Flexible 8- and 16-Bit asynchronous memory interface with up to four chip selectsSupports NOR, Muxed-NOR, SRAMSupports general-purpose memory-port expansion with the following modes:Asynchronous read and write accessAsynchronous read page access (4-, 8-, 16-Word16)Synchronous read and write accessSynchronous read burst access without wrap capability (4-, 8-, 16-Word16)Network Subsystem (NSS):Ethernet MAC (EMAC) subsystemOne-port Gigabit Ethernet: RMII, MII, RGMIISupports 10-, 100-, 1000-Mbps full duplexSupports 10-, 100-Mbps half duplexSupports Ethernet Audio Video Bridging (eAVB)Maximum frame size 2016 Bytes (2020 Bytes with VLAN)Eight priority level QOS support (802.1p)IEEE 1588v2 (2008 Annex D, Annex E, andAnnex F) to facilitate Audio Video Bridging 802.1AS Precision Time Protocol (PTP)CPTS module with timestamping support for IEEE 1588v2DSCP priority mapping (IPv4 and IPv6)MDIO module for PHY managementEnhanced statistics collectionNavigator Subsystem (NAVSS)Built-In packet DMA controller for optimized network processingBuilt-In Queue Manager (QM) for optimized network processingSupports up to 128 queues2048 buffers supported in internal queue RAMCrypto Engine (SA) supports:Crypto Function Library for AES, DES, 3DES, SHA1, MD5, SHA2-224 and SHA2-256 OperationsBlock data encryption supported through hardware coresAES with 128-, 192-, and 256-Bit Key supportsDES and 3DES with 1, 2, or 3 Different Key supportProgrammable Mode Control Engine (MCE)Public Key Accelerator (PKA) with elliptic curve cryptographyElliptic Curve Diffie–Hellman (ECDH) based key exchange and digital signature (ECDSA) applicationsAuthentication for SHA1, MD5, SHA2-224 and SHA2-256Keyed HMAC operation through hardware coreTrue Random Number Generator (TRNG)Display Subsystem:Supports one video pipe with in-loop scaling, color spaceConversion and background color overlayInput data format: BITMAP, RGB16, RGB24, RGB32, ARGB16, ARGB32, YUV420, YUV422, and RGB565-A8Supported display interfaces:MIPI®DPI 2.0 parallel interfaceRFBI (MIPI-DBI 2.0) up to QVGA at 30fpsBT.656 4:2:2BT.1120 4:2:2 up to 1920 × 1080 at 30fpsIn-loop scaling capabilityLCD interface supports:Active Matrix (TFT)Passive Matrix (STN)GrayscaleTDMAC Bias ControlDitherCPRAsynchronous Audio Sample Rate Converter (ASRC)High performance asynchronous sample rate converter with 140 dB Signal-to-Noise (SNR)Up to 8 stereo streams (16 audio channels)Automatically sensing / detection of input sample frequenciesAttenuation of sampling clock jitter16-, 18-, 20-, 24-Bit data input/outputAudio sample rates from 8 kHz to 216 kHzInput/output sampling ratios from 16:1 to 1:16Group mode, where multiple ASRC blocks use the same timing loop for input or outputLinear phase FIR filterControllable soft muteIndependent clock generator, and rate and stamp generator, for each input and output clock zoneSeparate DMA events for input and output, for each channel and groupHigh-speed serial interfaces:PCI Express®2.0 port with integrated PHY:Single lane Gen2-compliant portRoot Complex (RC) and End Point (EP) modesUp to two USB 2.0 High-Speed dual-role ports with Integrated PHYs, support:Dual-role-device (DRD) Capability with:USB 2.0 peripheral (or device) atHS (480Mbps) and FS (12Mbps) speedsUSB 2.0 host at HS (480Mbps),FS (12Mbps), and LS (1.5Mbps) speedsUSB 2.0 static peripheral and static host operationsxHCI controller with the following features:Compatible to the xHCI specification (revision 1.1) in host modeAll modes of transfer (control, bulk, interrupt, and isochronous)15 transmit (TX), 15 receive (RX) endpoints (EPs), and one bidirectional endpoint (EP0)Flash media interfaces:QSPI™ with XIP and up to four chip selects, supports:Memory-mapped direct mode of operation for performing FLASH data transfers and executing code from FLASH memory (XIP)Supports up to 96 MHzInternal SRAM buffer with ECCHigh speed read data capture mechanismTwo Multimedia Card (MMC) and Secure Digital (SD) portsSupports JEDEC JESD84 v4.5-A441 and SD3.0 physical layer with SDA3.00 standardsMMC0 supports 3.3-V I/O for:SD DS and HS modeeMMC mode HS-SDRup to 48 MHzMMC1 supports 1.8-V I/O modes for eMMC, including HS-SDR and DDR at up to 48 MHz with 4- and 8-Bit bus widthAudio peripherals:Three Multichannel Audio Serial Port (McASP) peripheralsTransmit and receive clocks up to 50 MHzTwo independent clock zones and independent transmit and receive clocks per McASPUp to 16-, 10-, 6-serial data pins for McASP0, McASP1, and McASP2, respectivelySupports TDM, I2S, and similar formatsSupports DIT modeBuilt-In FIFO buffers for optimized system trafficMultichannel Buffered Serial Port (McBSP)Transmit and receive clocks up to 50 MHzTwo clock zones and two serial-data pinsSupports TDM, I2S, and similar formatsReal-time control interfaces:Six Enhanced High Resolution Pulse Width Modulation (eHRPWM) Modules, Each Counter supports:Dedicated 16-Bit Time-Base with Period and Frequency ControlTwo independent PWM outputs with single edge operationTwo independent PWM outputs with dual-edge symmetric operationOne independent PWM output with dual-edge asymmetric operationTwo 32-Bit Enhanced Capture Modules (eCAP):Supports one capture input or one auxiliary PWM output configuration options4-Event time-stamp registers (Each 32-Bits)Interrupt on either of the four eventsThree 32-Bit Enhanced Quadrature Pulse Encoder Modules (eQEP), each supports:Quadrature decodingPosition counter and control unit for position measurementUnit time base for speed and frequency measurementGeneral connectivity:Two Controller Area Network (CAN) PortsSupports CAN v2.0 Part A, B (ISO 11898-1) protocolBit rates up to 1 MbpsDual clock sourceECC protection for message RAMOne Media Local Bus (MLB)Supports both 3-pin (up to MOST50, 1024 × Fs) and 6-pin (up to MOST150, 2048 × Fs) versions of MediaLB®Physical layer specification v4.2Supports all types of data transfer over 64 logical channels (synchronous stream, isochronous, asynchronous packet, control message)Supports 3-wire MOST 150 protocolThree Inter-Integrated Circuit (I2C) interfaces, each supports:Standard (up to 100 kHz) andFast (up to 400 kHz) modes7-Bit addressing modeSupports EEPROM size up to 4MbitFour Serial Peripheral Interfaces (SPI), each supports:Operates at up to 50 MHz in master mode and 25 MHz in slave modeTwo chip selectsThree UART interfacesAll UARTs are 16C750-compatible and operate at up to 3M baudUART0 supports 8 pins with full modem control, with DSR, DTR, DCD, and RI signalsUART1 and UART2 are 4-pin interfacesGeneral-Purpose I/O (GPIO)Up to 212 GPIOs muxed with other interfacesCan be configured as interrupt pinsTimers and miscellaneous modules:Seven 64-Bit timers:Two 64-Bit timers dedicated to Arm A15 and DSP cores (one timer per core)Watchdog and General-Purpose (GP)Four 64-Bit timers are shared for general purposesEach 64-Bit timer can be configured as two individual 32-Bit timersOne 64-Bit timer dedicated for PMMCTwo timers input/output pin pairsInterprocessor communication with:Message manager to facilitate multiprocessor access to the PMMC:Provides hardware acceleration for pushing and popping messages to/from logical queuesSupports up to 64 queues and 128 messagesSemaphore module with up to 64 independent semaphores and 16 masters (device cores)EDMA with 128 (2 × 64) channels and1024 (2 × 512) PaRAM entriesKeystone II System on Chip (SoC) architecture:SecuritySupports General-Purpose (GP) and High-Secure (HS) devicesSupports secure bootSupports customer secondary keys4KB of One-Time Programmable (OTP) ROM for customer keysPower managementIntegrated Power Management Microcontroller (PMMC) technologySupports primary boot from UART, I2C, SPI, GPMC, SD or eMMC, USB device firmware upgrade v1.1, PCIe®, and Ethernet interfacesKeystone II debug architecture with integrated Arm CoreSight™ support and trace capabilityOperating Temperature (TJ):–40°C to 125°C (Industrial Extended)–40°C to 105°C (Extended)0°C to 90°C (Commercial)Processor cores:Arm®Cortex®-A15 microprocessor unit (Arm A15) subsystem at up to 1000 MHzSupports full Implementation of Armv7-A architecture instruction setIntegrated SIMDv2 (Arm®Neon™ Technology) and VFPv4 (Vector Floating Point)32KB of L1 program memory32KB of L1 data memory512KB of L2 memoryError Correction Code (ECC) protection for L1 data memory ECC for L2 memoryParity protection for L1 program memoryGlobal Timebase Counter (GTC)64-Bit free-running counter that provides timebase for Arm A15 internal timersCompliant to Armv7 MPCore Architecture for Generic TimersC66x fixed- and floating-point VLIW DSP subsystem at up to 1000 MHzFully object-code compatible With C67x+ and C64x+ cores32KB of L1 program memory32KB of L1 data memory1024KB of L2 configurable as L2 RAM or cacheError detection for L1 program memoryECC for L1 data memoryECC for L2 data memoryIndustrial subsystem:Up to Two Programmable Real-Time Unit and Industrial Communication Subsystems (PRU-ICSS), each supports:Two Programmable Real-Time Units (PRUs) with enhanced multiplier and accumulator, each PRU supports:16KB of program memory With ECC8KB of data memory With ECCCRC32 and CRC16 hardware accelerator20 × enhanced GPIOSerial Capture Unit (SCU), supporting direct connection, 16-bit parallel capture, 28-bit shift, MII_RT, EnDat 2.2 protocol and Sigma-Delta demodulationScratch pad and XFR direct connect64KB of general-purpose memory With ECCOne Ethernet MII_RT module with two MII ports configurable for connection with each PRU; supports multiple industrial communication protocolsIndustrial Ethernet Peripheral (IEP) to manage and generate industrial Ethernet functionsBuilt-In Universal Asynchronous Receiver and Transmitter (UART) 16550, with a dedicated 192-MHz clock to support 12-Mbps PROFIBUS®Built-In industrial Ethernet 64-Bit timerBuilt-In enhanced capture module (eCAP)Memory subsystem:Multicore Shared Memory Controller (MSMC) with 1024KB of shared L2 RAMProvides high-performance interconnect to internal shared SRAM and DDR EMIF for both Arm A15 and C66x AccessSupports Arm I/O coherency where Arm A15 is cache coherent to other system masters accessing the MSMC-SRAM or DDR EMIFSupports ECC on SRAMUp to 36-Bit DDR External Memory Interface (EMIF)Supports DDR3L at up to 1066 MT/sSupports 4-GB memory address rangeSupports 32-Bit SDRAM data bus with 4-bit ECCSupports 16-Bit and 32-Bit SDRAM data bus without ECCGeneral-Purpose Memory Controller (GPMC)Flexible 8- and 16-Bit asynchronous memory interface with up to four chip selectsSupports NOR, Muxed-NOR, SRAMSupports general-purpose memory-port expansion with the following modes:Asynchronous read and write accessAsynchronous read page access (4-, 8-, 16-Word16)Synchronous read and write accessSynchronous read burst access without wrap capability (4-, 8-, 16-Word16)Network Subsystem (NSS):Ethernet MAC (EMAC) subsystemOne-port Gigabit Ethernet: RMII, MII, RGMIISupports 10-, 100-, 1000-Mbps full duplexSupports 10-, 100-Mbps half duplexSupports Ethernet Audio Video Bridging (eAVB)Maximum frame size 2016 Bytes (2020 Bytes with VLAN)Eight priority level QOS support (802.1p)IEEE 1588v2 (2008 Annex D, Annex E, andAnnex F) to facilitate Audio Video Bridging 802.1AS Precision Time Protocol (PTP)CPTS module with timestamping support for IEEE 1588v2DSCP priority mapping (IPv4 and IPv6)MDIO module for PHY managementEnhanced statistics collectionNavigator Subsystem (NAVSS)Built-In packet DMA controller for optimized network processingBuilt-In Queue Manager (QM) for optimized network processingSupports up to 128 queues2048 buffers supported in internal queue RAMCrypto Engine (SA) supports:Crypto Function Library for AES, DES, 3DES, SHA1, MD5, SHA2-224 and SHA2-256 OperationsBlock data encryption supported through hardware coresAES with 128-, 192-, and 256-Bit Key supportsDES and 3DES with 1, 2, or 3 Different Key supportProgrammable Mode Control Engine (MCE)Public Key Accelerator (PKA) with elliptic curve cryptographyElliptic Curve Diffie–Hellman (ECDH) based key exchange and digital signature (ECDSA) applicationsAuthentication for SHA1, MD5, SHA2-224 and SHA2-256Keyed HMAC operation through hardware coreTrue Random Number Generator (TRNG)Display Subsystem:Supports one video pipe with in-loop scaling, color spaceConversion and background color overlayInput data format: BITMAP, RGB16, RGB24, RGB32, ARGB16, ARGB32, YUV420, YUV422, and RGB565-A8Supported display interfaces:MIPI®DPI 2.0 parallel interfaceRFBI (MIPI-DBI 2.0) up to QVGA at 30fpsBT.656 4:2:2BT.1120 4:2:2 up to 1920 × 1080 at 30fpsIn-loop scaling capabilityLCD interface supports:Active Matrix (TFT)Passive Matrix (STN)GrayscaleTDMAC Bias ControlDitherCPRAsynchronous Audio Sample Rate Converter (ASRC)High performance asynchronous sample rate converter with 140 dB Signal-to-Noise (SNR)Up to 8 stereo streams (16 audio channels)Automatically sensing / detection of input sample frequenciesAttenuation of sampling clock jitter16-, 18-, 20-, 24-Bit data input/outputAudio sample rates from 8 kHz to 216 kHzInput/output sampling ratios from 16:1 to 1:16Group mode, where multiple ASRC blocks use the same timing loop for input or outputLinear phase FIR filterControllable soft muteIndependent clock generator, and rate and stamp generator, for each input and output clock zoneSeparate DMA events for input and output, for each channel and groupHigh-speed serial interfaces:PCI Express®2.0 port with integrated PHY:Single lane Gen2-compliant portRoot Complex (RC) and End Point (EP) modesUp to two USB 2.0 High-Speed dual-role ports with Integrated PHYs, support:Dual-role-device (DRD) Capability with:USB 2.0 peripheral (or device) atHS (480Mbps) and FS (12Mbps) speedsUSB 2.0 host at HS (480Mbps),FS (12Mbps), and LS (1.5Mbps) speedsUSB 2.0 static peripheral and static host operationsxHCI controller with the following features:Compatible to the xHCI specification (revision 1.1) in host modeAll modes of transfer (control, bulk, interrupt, and isochronous)15 transmit (TX), 15 receive (RX) endpoints (EPs), and one bidirectional endpoint (EP0)Flash media interfaces:QSPI™ with XIP and up to four chip selects, supports:Memory-mapped direct mode of operation for performing FLASH data transfers and executing code from FLASH memory (XIP)Supports up to 96 MHzInternal SRAM buffer with ECCHigh speed read data capture mechanismTwo Multimedia Card (MMC) and Secure Digital (SD) portsSupports JEDEC JESD84 v4.5-A441 and SD3.0 physical layer with SDA3.00 standardsMMC0 supports 3.3-V I/O for:SD DS and HS modeeMMC mode HS-SDRup to 48 MHzMMC1 supports 1.8-V I/O modes for eMMC, including HS-SDR and DDR at up to 48 MHz with 4- and 8-Bit bus widthAudio peripherals:Three Multichannel Audio Serial Port (McASP) peripheralsTransmit and receive clocks up to 50 MHzTwo independent clock zones and independent transmit and receive clocks per McASPUp to 16-, 10-, 6-serial data pins for McASP0, McASP1, and McASP2, respectivelySupports TDM, I2S, and similar formatsSupports DIT modeBuilt-In FIFO buffers for optimized system trafficMultichannel Buffered Serial Port (McBSP)Transmit and receive clocks up to 50 MHzTwo clock zones and two serial-data pinsSupports TDM, I2S, and similar formatsReal-time control interfaces:Six Enhanced High Resolution Pulse Width Modulation (eHRPWM) Modules, Each Counter supports:Dedicated 16-Bit Time-Base with Period and Frequency ControlTwo independent PWM outputs with single edge operationTwo independent PWM outputs with dual-edge symmetric operationOne independent PWM output with dual-edge asymmetric operationTwo 32-Bit Enhanced Capture Modules (eCAP):Supports one capture input or one auxiliary PWM output configuration options4-Event time-stamp registers (Each 32-Bits)Interrupt on either of the four eventsThree 32-Bit Enhanced Quadrature Pulse Encoder Modules (eQEP), each supports:Quadrature decodingPosition counter and control unit for position measurementUnit time base for speed and frequency measurementGeneral connectivity:Two Controller Area Network (CAN) PortsSupports CAN v2.0 Part A, B (ISO 11898-1) protocolBit rates up to 1 MbpsDual clock sourceECC protection for message RAMOne Media Local Bus (MLB)Supports both 3-pin (up to MOST50, 1024 × Fs) and 6-pin (up to MOST150, 2048 × Fs) versions of MediaLB®Physical layer specification v4.2Supports all types of data transfer over 64 logical channels (synchronous stream, isochronous, asynchronous packet, control message)Supports 3-wire MOST 150 protocolThree Inter-Integrated Circuit (I2C) interfaces, each supports:Standard (up to 100 kHz) andFast (up to 400 kHz) modes7-Bit addressing modeSupports EEPROM size up to 4MbitFour Serial Peripheral Interfaces (SPI), each supports:Operates at up to 50 MHz in master mode and 25 MHz in slave modeTwo chip selectsThree UART interfacesAll UARTs are 16C750-compatible and operate at up to 3M baudUART0 supports 8 pins with full modem control, with DSR, DTR, DCD, and RI signalsUART1 and UART2 are 4-pin interfacesGeneral-Purpose I/O (GPIO)Up to 212 GPIOs muxed with other interfacesCan be configured as interrupt pinsTimers and miscellaneous modules:Seven 64-Bit timers:Two 64-Bit timers dedicated to Arm A15 and DSP cores (one timer per core)Watchdog and General-Purpose (GP)Four 64-Bit timers are shared for general purposesEach 64-Bit timer can be configured as two individual 32-Bit timersOne 64-Bit timer dedicated for PMMCTwo timers input/output pin pairsInterprocessor communication with:Message manager to facilitate multiprocessor access to the PMMC:Provides hardware acceleration for pushing and popping messages to/from logical queuesSupports up to 64 queues and 128 messagesSemaphore module with up to 64 independent semaphores and 16 masters (device cores)EDMA with 128 (2 × 64) channels and1024 (2 × 512) PaRAM entriesKeystone II System on Chip (SoC) architecture:SecuritySupports General-Purpose (GP) and High-Secure (HS) devicesSupports secure bootSupports customer secondary keys4KB of One-Time Programmable (OTP) ROM for customer keysPower managementIntegrated Power Management Microcontroller (PMMC) technologySupports primary boot from UART, I2C, SPI, GPMC, SD or eMMC, USB device firmware upgrade v1.1, PCIe®, and Ethernet interfacesKeystone II debug architecture with integrated Arm CoreSight™ support and trace capabilityOperating Temperature (TJ):–40°C to 125°C (Industrial Extended)–40°C to 105°C (Extended)0°C to 90°C (Commercial)
Description
AI
66AK2G1x is a family of heterogeneous multicore System-on-Chip (SoC) devices based on TI’s field-proven Keystone II (KS2) architecture. These devices address applications that require both DSP and Arm performance, with integration of high-speed peripheral and memory interfaces, hardware acceleration for network and cryptography functions, and high-level operating systems (HLOS) support.
Similar to existing KS2-based SoC devices, the 66AK2G1x enables both the DSP and Arm cores to master all memory and peripherals in the system. This architecture facilitates maximum software flexibility where either DSP- or Arm-centric system designs can be achieved.
The 66AK2G1x significantly improves device reliability by extensively implementing error correction code (ECC) in processor cores, shared memory, embedded memory in modules, and external memory interfaces. Full analysis of soft error rate (SER) and power-on-hours (POH) shows that the designated 66AK2G1x parts satisfy a wide range of industrial requirements.
Accompanied by the new Processor SDK, the 66AK2G1x development platform enables unprecedented ease-of-use with main line open source Linux, Code Composer Studio™ (CCS) - Integrated Development Environment (IDE), a wide range of OS-independent device drivers, as well as TI-RTOS that enables seamless task management across processor cores. The device also features advanced debug and trace technology with the latest innovations from TI and Arm, such as system trace and seamless integration of the Arm CoreSight components.
Secure boot can also be made available for anticloning and illegal software update protection. For more information about secure boot, contact your TI sales representative.
66AK2G1x is a family of heterogeneous multicore System-on-Chip (SoC) devices based on TI’s field-proven Keystone II (KS2) architecture. These devices address applications that require both DSP and Arm performance, with integration of high-speed peripheral and memory interfaces, hardware acceleration for network and cryptography functions, and high-level operating systems (HLOS) support.
Similar to existing KS2-based SoC devices, the 66AK2G1x enables both the DSP and Arm cores to master all memory and peripherals in the system. This architecture facilitates maximum software flexibility where either DSP- or Arm-centric system designs can be achieved.
The 66AK2G1x significantly improves device reliability by extensively implementing error correction code (ECC) in processor cores, shared memory, embedded memory in modules, and external memory interfaces. Full analysis of soft error rate (SER) and power-on-hours (POH) shows that the designated 66AK2G1x parts satisfy a wide range of industrial requirements.
Accompanied by the new Processor SDK, the 66AK2G1x development platform enables unprecedented ease-of-use with main line open source Linux, Code Composer Studio™ (CCS) - Integrated Development Environment (IDE), a wide range of OS-independent device drivers, as well as TI-RTOS that enables seamless task management across processor cores. The device also features advanced debug and trace technology with the latest innovations from TI and Arm, such as system trace and seamless integration of the Arm CoreSight components.
Secure boot can also be made available for anticloning and illegal software update protection. For more information about secure boot, contact your TI sales representative.