CD74HCT107 Series
High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset
| Part | Number of Elements [custom] | Number of Bits per Element | Package / Case | Package / Case | Package / Case | Output Type | Function | Current - Output High, Low | Type | Input Capacitance | Voltage - Supply [Max] | Voltage - Supply [Min] | Max Propagation Delay @ V, Max CL | Trigger Type | Clock Frequency | Mounting Type | Current - Quiescent (Iq) | Operating Temperature [Min] | Operating Temperature [Max] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD74HCT107E | 2 | 1 | 14-DIP | 7.62 mm | 0.3 in | Complementary | Reset | 4 mA, 4 mA | JK Type | 10 pF | 5.5 V | 4.5 V | 43 ns | Negative Edge | 56 MHz | Through Hole | 4 çA | -55 C | 125 °C |
Key Features
• Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall TimesAsynchronous ResetComplementary OutputsBuffered InputsTypical fMAX= 60MHz at VCC= 5V, CL= 15pF, TA= 25°CFanout (Over Temperature Range)Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . -55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOHHysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall TimesAsynchronous ResetComplementary OutputsBuffered InputsTypical fMAX= 60MHz at VCC= 5V, CL= 15pF, TA= 25°CFanout (Over Temperature Range)Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . -55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOH
Description
AI
The ’HC107 and ’HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
These flip-flops have independent J, K, Reset and Clock inputs and Q and Q\ outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input.
This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits.
The HCT logic family is functionally as well as pin compatible with the standard LS family.
The ’HC107 and ’HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
These flip-flops have independent J, K, Reset and Clock inputs and Q and Q\ outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input.
This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits.
The HCT logic family is functionally as well as pin compatible with the standard LS family.