Catalog(1 parts)
| Part | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Operating Temperature▲▼ | Operating Temperature▲▼ | Function | Package / Case▲▼ | Package / Case▲▼ | Package / Case | Trigger Type | Number of Bits per Element▲▼ | Current - Quiescent (Iq)▲▼ | Max Propagation Delay @ V, Max CL▲▼ | Number of Elements▲▼ | Mounting Type | Output Type | Clock Frequency▲▼ | Current - Output High, Low▲▼ | Current - Output High, Low▲▼ | Type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments SN74LS107ADFlip Flop 2 Element JK Type 1 Bit Negative Edge 14-SOIC (0.154", 3.90mm Width) | 4.75 V | 5.25 V | 70 °C | 0 °C | Reset | 0.003899999894201755 m | 0.003911599982529879 m | 14-SOIC | Negative Edge | 1 ul | 0.006000000052154064 A | 1.999999987845058e-8 s | 2 ul | Surface Mount | Complementary | 45000000 Hz | 0.00800000037997961 A | 0.00039999998989515007 A | JK Type |
Key Features
• Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPsDependable Texas Instruments Quality and ReliabilityPackage Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPsDependable Texas Instruments Quality and Reliability
Description
AI
The '107 contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '107 is a positive pulse-triggered flip-flop. The J-K input data is loaded into the master while the clock is high and transferred to the slave and the outputs on the high-to-low clock transition. For these devices the J and K inputs must be stable while the clock is high.
The 'LS107A contain two independent negative-edge-triggered flip-flops. The J and K inputs must be stable prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.
The SN54107 and the SN54LS107A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74107 and the SN74LS107A are characterized for operation from 0°C to 70°C.
The '107 contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '107 is a positive pulse-triggered flip-flop. The J-K input data is loaded into the master while the clock is high and transferred to the slave and the outputs on the high-to-low clock transition. For these devices the J and K inputs must be stable while the clock is high.
The 'LS107A contain two independent negative-edge-triggered flip-flops. The J and K inputs must be stable prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.
The SN54107 and the SN54LS107A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74107 and the SN74LS107A are characterized for operation from 0°C to 70°C.