74HC40105 Series

High Speed CMOS Logic 4-Bit by 16-Word FIFO Register

Catalog(3 parts)

Part	Bus Directional	Mounting Type	Supplier Device Package	Expansion Type	Voltage - Supply▲▼	Voltage - Supply▲▼	Operating Temperature▲▼	Operating Temperature▲▼	Function	Memory Size▲▼	Package / Case	Package / Case▲▼
Texas Instruments CD74HC40105M96 Asynchronous FIFO 64 (16 x 4) Uni-Directional 16-SOIC	Uni-Directional	Surface Mount	16-SOIC	Depth, Width	6 V	2 V	-55 °C	125 °C	Asynchronous	64 ul	16-SOIC	0.003911599982529879 m, 3.900000095367432 ul
Texas Instruments CD74HC40105MT Asynchronous FIFO 64 (16 x 4) Uni-Directional 16-SOIC	Uni-Directional	Surface Mount	16-SOIC	Depth, Width	6 V	2 V	-55 °C	125 °C	Asynchronous	64 ul	16-SOIC	0.003911599982529879 m, 3.900000095367432 ul
Texas Instruments CD74HC40105E Asynchronous FIFO 64 (16 x 4) Uni-Directional 16-PDIP	Uni-Directional	Through Hole	16-PDIP	Depth, Width	6 V	2 V	-55 °C	125 °C	Asynchronous	64 ul	16-DIP	0.007619999814778566 m, 0.007619999814778566 m

Key Features

• Independent Asynchronous Inputs and OutputsExpandable in Either DirectionReset CapabilityStatus Indicators on Inputs and OutputsThree-State OutputsShift-Out Independent of Three-State ControlFanout (Over Temperature Range)Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . -55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il≤ 1µA at VOL, VOHApplicationsBit-Rate SmoothingCPU/Terminal BufferingData CommunicationsPeripheral BufferingLine Printer Input BuffersAuto-DialersCRT Buffer MemoriesRadar Data AcquisitionIndependent Asynchronous Inputs and OutputsExpandable in Either DirectionReset CapabilityStatus Indicators on Inputs and OutputsThree-State OutputsShift-Out Independent of Three-State ControlFanout (Over Temperature Range)Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . -55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il≤ 1µA at VOL, VOHApplicationsBit-Rate SmoothingCPU/Terminal BufferingData CommunicationsPeripheral BufferingLine Printer Input BuffersAuto-DialersCRT Buffer MemoriesRadar Data Acquisition

Description

The ’HC40105 and ’HCT40105 are high-speed silicon-gate CMOS devices that are compatible, except for "shift-out" circuitry, with the CD40105B. They are low-power first-in-out (FIFO) "elastic" storage registers that can store 16 four-bit words. The 40105 is capable of handling input and output data at different shifting rates. This feature makes particularly useful as a buffer between asynchronous systems. Each work position in the register is clocked by a control flip-flop, which stores a marker bit. A "1" signifies that the position’s data is filled and a "0" denotes a vacancy in that position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the "0" state and sees a "1" in the preceeding flip-flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to "0". The first and last control flip-flops have buffered outputs. Since all empty locations "bubble" automatically to the input end, and all valid data ripple through to the output end, the status of the first control flip-flop (DATA-IN READY) indicates if the FIFO is full, and the status of the last flip-flop (DATA-OUT READY) indicates if the FIFO contains data. As the earliest data are removed from the bottom of the data stack (the output end), all data entered later will automatically propagate (ripple) toward the output. The ’HC40105 and ’HCT40105 are high-speed silicon-gate CMOS devices that are compatible, except for "shift-out" circuitry, with the CD40105B. They are low-power first-in-out (FIFO) "elastic" storage registers that can store 16 four-bit words. The 40105 is capable of handling input and output data at different shifting rates. This feature makes particularly useful as a buffer between asynchronous systems. Each work position in the register is clocked by a control flip-flop, which stores a marker bit. A "1" signifies that the position’s data is filled and a "0" denotes a vacancy in that position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the "0" state and sees a "1" in the preceeding flip-flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to "0". The first and last control flip-flops have buffered outputs. Since all empty locations "bubble" automatically to the input end, and all valid data ripple through to the output end, the status of the first control flip-flop (DATA-IN READY) indicates if the FIFO is full, and the status of the last flip-flop (DATA-OUT READY) indicates if the FIFO contains data. As the earliest data are removed from the bottom of the data stack (the output end), all data entered later will automatically propagate (ripple) toward the output.