AM3352 Series
Sitara processor: Arm Cortex-A8, 1Gb Ethernet, display, CAN
Manufacturer: Texas Instruments
Catalog(14 parts)
| Part | Operating Temperature▲▼ | Operating Temperature▲▼ | Additional Interfaces | RAM Controllers | Display & Interface Controllers | Co-Processors/DSP | Graphics Acceleration▲▼ | Ethernet | Security Features | Number of Cores/Bus Width▲▼ | USB | Supplier Device Package | Core Processor | Package / Case | Speed▲▼ | Mounting Type | Voltage - I/O▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments AM3352BZCZD60ARM® Cortex®-A8 Microprocessor IC Sitara™ 1 Core, 32-Bit 600MHz 324-NFBGA (15x15) | -40 °C | 90 °C | CAN, I2C, McASP, McSPI, MMC/SD/SDIO, UART | DDR2, DDR3, DDR3L, LPDDR | LCD, Touchscreen | Multimedia, NEON™ SIMD | 10/100/1000Mbps (2) | Cryptography, Random Number Generator | 1 ul, 32 b | USB 2.0 + PHY (2) | 324-NFBGA (15x15) | ARM® Cortex®-A8 | 324-LFBGA | 600000000 Hz | Surface Mount | 1.7999999523162842 V, 3.299999952316284 V | |
Texas Instruments AM3352BZCZ100ARM® Cortex®-A8 Microprocessor IC Sitara™ 1 Core, 32-Bit 1.0GHz 324-NFBGA (15x15) | 0 °C | 90 °C | CAN, I2C, McASP, McSPI, MMC/SD/SDIO, UART | DDR2, DDR3, DDR3L, LPDDR | LCD, Touchscreen | Multimedia, NEON™ SIMD | 10/100/1000Mbps (2) | Cryptography, Random Number Generator | 1 ul, 32 b | USB 2.0 + PHY (2) | 324-NFBGA (15x15) | ARM® Cortex®-A8 | 324-LFBGA | 1000000000 Hz | Surface Mount | 1.7999999523162842 V, 3.299999952316284 V | |
Texas Instruments AM3352BZCZA60ARM® Cortex®-A8 Microprocessor IC Sitara™ 1 Core, 32-Bit 600MHz 324-NFBGA (15x15) | -40 °C | 105 °C | CAN, I2C, McASP, McSPI, MMC/SD/SDIO, UART | DDR2, DDR3, DDR3L, LPDDR | LCD, Touchscreen | Multimedia, NEON™ SIMD | 10/100/1000Mbps (2) | Cryptography, Random Number Generator | 1 ul, 32 b | USB 2.0 + PHY (2) | 324-NFBGA (15x15) | ARM® Cortex®-A8 | 324-LFBGA | 600000000 Hz | Surface Mount | 1.7999999523162842 V, 3.299999952316284 V | |
Texas Instruments AM3352BZCZ30ARM® Cortex®-A8 Microprocessor IC Sitara™ 1 Core, 32-Bit 300MHz 324-NFBGA (15x15) | 0 °C | 90 °C | CAN, I2C, McASP, McSPI, MMC/SD/SDIO, UART | DDR2, DDR3, DDR3L, LPDDR | LCD, Touchscreen | Multimedia, NEON™ SIMD | 10/100/1000Mbps (2) | Cryptography, Random Number Generator | 1 ul, 32 b | USB 2.0 + PHY (2) | 324-NFBGA (15x15) | ARM® Cortex®-A8 | 324-LFBGA | 300000000 Hz | Surface Mount | 1.7999999523162842 V, 3.299999952316284 V | |
Texas Instruments AM3352ZCZ60ARM® Cortex®-A8 Microprocessor IC Sitara™ 1 Core, 32-Bit 600MHz 324-NFBGA (15x15) | 0 °C | 90 °C | CAN, I2C, McASP, McSPI, MMC/SD/SDIO, UART | DDR2, DDR3, DDR3L, LPDDR | LCD, Touchscreen | Multimedia, NEON™ SIMD | 10/100/1000Mbps (2) | Cryptography, Random Number Generator | 1 ul, 32 b | USB 2.0 + PHY (2) | 324-NFBGA (15x15) | ARM® Cortex®-A8 | 324-LFBGA | 600000000 Hz | Surface Mount | 1.7999999523162842 V, 3.299999952316284 V | |
Texas Instruments AM3352BZCE60ARM® Cortex®-A8 Microprocessor IC Sitara™ 1 Core, 32-Bit 600MHz 298-NFBGA (13x13) | 0 °C | 90 °C | CAN, I2C, McASP, McSPI, MMC/SD/SDIO, UART | DDR2, DDR3, DDR3L, LPDDR | LCD, Touchscreen | Multimedia, NEON™ SIMD | 10/100/1000Mbps (1) | Cryptography, Random Number Generator | 1 ul, 32 b | USB 2.0 + PHY (1) | 298-NFBGA (13x13) | ARM® Cortex®-A8 | 298-LFBGA | 600000000 Hz | Surface Mount | 1.7999999523162842 V, 3.299999952316284 V | |
Texas Instruments AM3352BZCZA80ARM® Cortex®-A8 Microprocessor IC Sitara™ 1 Core, 32-Bit 800MHz 324-NFBGA (15x15) | -40 °C | 105 °C | CAN, I2C, McASP, McSPI, MMC/SD/SDIO, UART | DDR2, DDR3, DDR3L, LPDDR | LCD, Touchscreen | Multimedia, NEON™ SIMD | 10/100/1000Mbps (2) | Cryptography, Random Number Generator | 1 ul, 32 b | USB 2.0 + PHY (2) | 324-NFBGA (15x15) | ARM® Cortex®-A8 | 324-LFBGA | 800000000 Hz | Surface Mount | 1.7999999523162842 V, 3.299999952316284 V | |
Texas Instruments AM3352BZCEA60ARM® Cortex®-A8 Microprocessor IC Sitara™ 1 Core, 32-Bit 600MHz 298-NFBGA (13x13) | -40 °C | 105 °C | CAN, I2C, McASP, McSPI, MMC/SD/SDIO, UART | DDR2, DDR3, DDR3L, LPDDR | LCD, Touchscreen | Multimedia, NEON™ SIMD | 10/100/1000Mbps (2) | Cryptography, Random Number Generator | 1 ul, 32 b | USB 2.0 + PHY (2) | 298-NFBGA (13x13) | ARM® Cortex®-A8 | 298-LFBGA | 600000000 Hz | Surface Mount | 1.7999999523162842 V, 3.299999952316284 V | |
Texas Instruments AM3352BZCED30ARM® Cortex®-A8 Microprocessor IC Sitara™ 1 Core, 32-Bit 300MHz 298-NFBGA (13x13) | -40 °C | 90 °C | CAN, I2C, McASP, McSPI, MMC/SD/SDIO, UART | DDR2, DDR3, DDR3L, LPDDR | LCD, Touchscreen | Multimedia, NEON™ SIMD | 10/100/1000Mbps (2) | Cryptography, Random Number Generator | 1 ul, 32 b | USB 2.0 + PHY (2) | 298-NFBGA (13x13) | ARM® Cortex®-A8 | 298-LFBGA | 300000000 Hz | Surface Mount | 1.7999999523162842 V, 3.299999952316284 V | |
Texas Instruments AM3352BZCEA30RARM® Cortex®-A8 Microprocessor IC Sitara™ 1 Core, 32-Bit 300MHz 298-NFBGA (13x13) | -40 °C | 105 °C | CAN, I2C, McASP, McSPI, MMC/SD/SDIO, UART | DDR2, DDR3, DDR3L, LPDDR | LCD, Touchscreen | Multimedia, NEON™ SIMD | 10/100/1000Mbps (2) | Cryptography, Random Number Generator | 1 ul, 32 b | USB 2.0 + PHY (2) | 298-NFBGA (13x13) | ARM® Cortex®-A8 | 298-LFBGA | 300000000 Hz | Surface Mount | 1.7999999523162842 V, 3.299999952316284 V | |
Texas Instruments AM3352ZCE50ARM® Cortex®-A8 Microprocessor IC Sitara™ 1 Core, 32-Bit 500MHz 298-NFBGA (13x13) | 0 °C | 90 °C | CAN, I2C, McASP, McSPI, MMC/SD/SDIO, UART | DDR2, DDR3, DDR3L, LPDDR | LCD, Touchscreen | Multimedia, NEON™ SIMD | 10/100/1000Mbps (2) | Cryptography, Random Number Generator | 1 ul, 32 b | USB 2.0 + PHY (2) | 298-NFBGA (13x13) | ARM® Cortex®-A8 | 298-LFBGA | 500000000 Hz | Surface Mount | 1.7999999523162842 V, 3.299999952316284 V | |
Texas Instruments AM3352BZCE30ARM® Cortex®-A8 Microprocessor IC Sitara™ 1 Core, 32-Bit 300MHz 298-NFBGA (13x13) | 0 °C | 90 °C | CAN, I2C, McASP, McSPI, MMC/SD/SDIO, UART | DDR2, DDR3, DDR3L, LPDDR | LCD, Touchscreen | Multimedia, NEON™ SIMD | 10/100/1000Mbps (2) | Cryptography, Random Number Generator | 1 ul, 32 b | USB 2.0 + PHY (2) | 298-NFBGA (13x13) | ARM® Cortex®-A8 | 298-LFBGA | 300000000 Hz | Surface Mount | 1.7999999523162842 V, 3.299999952316284 V | |
-40 °C | 105 °C | CAN, I2C, McASP, McSPI, MMC/SD/SDIO, UART | DDR2, DDR3, DDR3L, LPDDR | LCD, Touchscreen | Multimedia, NEON™ SIMD | 10/100/1000Mbps (2) | Cryptography, Random Number Generator | 1 ul, 32 b | USB 2.0 + PHY (2) | ARM® Cortex®-A8 | 1.7999999523162842 V, 3.299999952316284 V | ||||||
Texas Instruments AM3352ZCED50ARM® Cortex®-A8 Microprocessor IC Sitara™ 1 Core, 32-Bit 500MHz 298-NFBGA (13x13) | -40 °C | 90 °C | CAN, I2C, McASP, McSPI, MMC/SD/SDIO, UART | DDR2, DDR3, DDR3L, LPDDR | LCD, Touchscreen | Multimedia, NEON™ SIMD | 10/100/1000Mbps (2) | Cryptography, Random Number Generator | 1 ul, 32 b | USB 2.0 + PHY (2) | 298-NFBGA (13x13) | ARM® Cortex®-A8 | 298-LFBGA | 500000000 Hz | Surface Mount | 1.7999999523162842 V, 3.299999952316284 V |
Key Features
• Up to 1-GHz Sitara™ ARM®Cortex®-A8 32‑Bit RISC ProcessorNEON™ SIMD Coprocessor32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity)256KB of L2 Cache With Error Correcting Code (ECC)176KB of On-Chip Boot ROM64KB of Dedicated RAMEmulation and Debug - JTAGInterrupt Controller (up to 128 Interrupt Requests)On-Chip Memory (Shared L3 RAM)64KB of General-Purpose On-Chip Memory Controller (OCMC) RAMAccessible to All MastersSupports Retention for Fast WakeupExternal Memory Interfaces (EMIF)mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:mDDR: 200-MHz Clock (400-MHz Data Rate)DDR2: 266-MHz Clock (532-MHz Data Rate)DDR3: 400-MHz Clock (800-MHz Data Rate)DDR3L: 400-MHz Clock (800-MHz Data Rate)16-Bit Data Bus1GB of Total Addressable SpaceSupports One x16 or Two x8 Memory Device ConfigurationsGeneral-Purpose Memory Controller (GPMC)Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)Uses BCH Code to Support 4-, 8-, or 16-Bit ECCUses Hamming Code to Support 1-Bit ECCError Locator Module (ELM)Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH AlgorithmSupports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH AlgorithmsProgrammable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)Supports Protocols such as EtherCAT®, PROFIBUS, PROFINET, EtherNet/IP™, and MoreTwo Programmable Real-Time Units (PRUs)32-Bit Load/Store RISC Processor Capable of Running at 200 MHz8KB of Instruction RAM With Single-Error Detection (Parity)8KB of Data RAM With Single-Error Detection (Parity)Single-Cycle 32-Bit Multiplier With 64-Bit AccumulatorEnhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal12KB of Shared RAM With Single-Error Detection (Parity)Three 120-Byte Register Banks Accessible by Each PRUInterrupt Controller (INTC) for Handling System Input EventsLocal Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSSPeripherals Inside the PRU-ICSS:One UART Port With Flow Control Pins, Supports up to 12 MbpsOne Enhanced Capture (eCAP) ModuleTwo MII Ethernet Ports that Support Industrial Ethernet, such as EtherCATOne MDIO PortPower, Reset, and Clock Management (PRCM) ModuleControls the Entry and Exit of Stand-By and Deep-Sleep ModesResponsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On SequencingClocksIntegrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral ClocksSupports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power ConsumptionFive ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock)PowerTwo Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKEUP])Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX], Peripherals and Infrastructure [PER])Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])Dynamic Voltage Frequency Scaling (DVFS)Real-Time Clock (RTC)Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) InformationInternal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDOIndependent Power-on-Reset (RTC_PWRONRSTn) InputDedicated Input Pin (EXT_WAKEUP) for External Wake EventsProgrammable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power DomainsPeripheralsUp to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports With Integrated PHYUp to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)Integrated SwitchEach MAC Supports MII, RMII, RGMII, and MDIO InterfacesEthernet MACs and Switch Can Operate Independent of Other FunctionsIEEE 1588v1 Precision Time Protocol (PTP)Up to Two Controller-Area Network (CAN) PortsSupports CAN Version 2 Parts A and BUp to Two Multichannel Audio Serial Ports (McASPs)Transmit and Receive Clocks up to 50 MHzUp to Four Serial Data Pins per McASP Port With Independent TX and RX ClocksSupports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar FormatsSupports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)FIFO Buffers for Transmit and Receive (256 Bytes)Up to Six UARTsAll UARTs Support IrDA and CIR ModesAll UARTs Support RTS and CTS Flow ControlUART1 Supports Full Modem ControlUp to Two Master and Slave McSPI Serial InterfacesUp to Two Chip SelectsUp to 48 MHzUp to Three MMC, SD, SDIO Ports1-, 4- and 8-Bit MMC, SD, SDIO ModesMMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V OperationUp to 48-MHz Data Transfer RateSupports Card Detect and Write ProtectComplies With MMC4.3, SD, SDIO 2.0 SpecificationsUp to Three I2C Master and Slave InterfacesStandard Mode (up to 100 kHz)Fast Mode (up to 400 kHz)Up to Four Banks of General-Purpose I/O (GPIO) Pins32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)Up to Three External DMA Event Inputs that can Also be Used as Interrupt InputsEight 32-Bit General-Purpose TimersDMTIMER1 is a 1-ms Timer Used for Operating System (OS) TicksDMTIMER4–DMTIMER7 are Pinned OutOne Watchdog TimerSGX530 3D Graphics EngineTile-Based Architecture Delivering up to 20 Million Polygons per SecondUniversal Scalable Shader Engine (USSE) is a Multithreaded Engine Incorporating Pixel and Vertex Shader FunctionalityAdvanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0, and OpenMaxFine-Grained Task Switching, Load Balancing, and Power ManagementAdvanced Geometry DMA-Driven Operation for Minimum CPU InteractionProgrammable High-Quality Image Anti-AliasingFully Virtualized Memory Addressing for OS Operation in a Unified Memory ArchitectureLCD ControllerUp to 24-Bit Data Output; 8 Bits per Pixel (RGB)Resolution up to 2048 × 2048 (With Maximum 126-MHz Pixel Clock)Integrated LCD Interface Display Driver (LIDD) ControllerIntegrated Raster ControllerIntegrated DMA Engine to Pull Data from the External Frame Buffer Without Burdening the Processor via Interrupts or a Firmware Timer512-Word Deep Internal FIFOSupported Display Types:Character Displays - Uses LIDD Controller to Program these DisplaysPassive Matrix LCD Displays - Uses LCD Raster Display Controller to Provide Timing and Data for Constant Graphics Refresh to a Passive DisplayActive Matrix LCD Displays - Uses External Frame Buffer Space and the Internal DMA Engine to Drive Streaming Data to the Panel12-Bit Successive Approximation Register (SAR) ADC200K Samples per SecondInput can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog SwitchCan be Configured to Operate as a 4-Wire, 5-Wire, or 8-Wire Resistive Touch Screen Controller (TSC) InterfaceUp to Three 32-Bit eCAP ModulesConfigurable as Three Capture Inputs or Three Auxiliary PWM OutputsUp to Three Enhanced High-Resolution PWM Modules (eHRPWMs)Dedicated 16-Bit Time-Base Counter With Time and Frequency ControlsConfigurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric OutputsUp to Three 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) ModulesDevice IdentificationContains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory ProgrammableProduction IDDevice Part Number (Unique JTAG ID)Device Revision (Readable by Host ARM)Debug Interface SupportJTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS DebugSupports Device Boundary ScanSupports IEEE 1500DMAOn-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:Transfers to and from On-Chip MemoriesTransfers to and from External Storage (EMIF, GPMC, Slave Peripherals)Inter-Processor Communication (IPC)Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSSMailbox Registers that Generate InterruptsFour Initiators (Cortex-A8, PRCM, PRU0, PRU1)Spinlock has 128 Software-Assigned Lock RegistersSecurityCrypto Hardware Accelerators (AES, SHA, RNG)Secure Boot (optional; requires custom part engagement with TI)Boot ModesBoot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input PinPackages:298-Pin S-PBGA-N298 Via Channel Package(ZCE Suffix), 0.65-mm Ball Pitch324-Pin S-PBGA-N324 Package(ZCZ Suffix), 0.80-mm Ball PitchUp to 1-GHz Sitara™ ARM®Cortex®-A8 32‑Bit RISC ProcessorNEON™ SIMD Coprocessor32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity)256KB of L2 Cache With Error Correcting Code (ECC)176KB of On-Chip Boot ROM64KB of Dedicated RAMEmulation and Debug - JTAGInterrupt Controller (up to 128 Interrupt Requests)On-Chip Memory (Shared L3 RAM)64KB of General-Purpose On-Chip Memory Controller (OCMC) RAMAccessible to All MastersSupports Retention for Fast WakeupExternal Memory Interfaces (EMIF)mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:mDDR: 200-MHz Clock (400-MHz Data Rate)DDR2: 266-MHz Clock (532-MHz Data Rate)DDR3: 400-MHz Clock (800-MHz Data Rate)DDR3L: 400-MHz Clock (800-MHz Data Rate)16-Bit Data Bus1GB of Total Addressable SpaceSupports One x16 or Two x8 Memory Device ConfigurationsGeneral-Purpose Memory Controller (GPMC)Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)Uses BCH Code to Support 4-, 8-, or 16-Bit ECCUses Hamming Code to Support 1-Bit ECCError Locator Module (ELM)Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH AlgorithmSupports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH AlgorithmsProgrammable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)Supports Protocols such as EtherCAT®, PROFIBUS, PROFINET, EtherNet/IP™, and MoreTwo Programmable Real-Time Units (PRUs)32-Bit Load/Store RISC Processor Capable of Running at 200 MHz8KB of Instruction RAM With Single-Error Detection (Parity)8KB of Data RAM With Single-Error Detection (Parity)Single-Cycle 32-Bit Multiplier With 64-Bit AccumulatorEnhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal12KB of Shared RAM With Single-Error Detection (Parity)Three 120-Byte Register Banks Accessible by Each PRUInterrupt Controller (INTC) for Handling System Input EventsLocal Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSSPeripherals Inside the PRU-ICSS:One UART Port With Flow Control Pins, Supports up to 12 MbpsOne Enhanced Capture (eCAP) ModuleTwo MII Ethernet Ports that Support Industrial Ethernet, such as EtherCATOne MDIO PortPower, Reset, and Clock Management (PRCM) ModuleControls the Entry and Exit of Stand-By and Deep-Sleep ModesResponsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On SequencingClocksIntegrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral ClocksSupports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power ConsumptionFive ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock)PowerTwo Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKEUP])Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX], Peripherals and Infrastructure [PER])Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])Dynamic Voltage Frequency Scaling (DVFS)Real-Time Clock (RTC)Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) InformationInternal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDOIndependent Power-on-Reset (RTC_PWRONRSTn) InputDedicated Input Pin (EXT_WAKEUP) for External Wake EventsProgrammable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power DomainsPeripheralsUp to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports With Integrated PHYUp to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)Integrated SwitchEach MAC Supports MII, RMII, RGMII, and MDIO InterfacesEthernet MACs and Switch Can Operate Independent of Other FunctionsIEEE 1588v1 Precision Time Protocol (PTP)Up to Two Controller-Area Network (CAN) PortsSupports CAN Version 2 Parts A and BUp to Two Multichannel Audio Serial Ports (McASPs)Transmit and Receive Clocks up to 50 MHzUp to Four Serial Data Pins per McASP Port With Independent TX and RX ClocksSupports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar FormatsSupports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)FIFO Buffers for Transmit and Receive (256 Bytes)Up to Six UARTsAll UARTs Support IrDA and CIR ModesAll UARTs Support RTS and CTS Flow ControlUART1 Supports Full Modem ControlUp to Two Master and Slave McSPI Serial InterfacesUp to Two Chip SelectsUp to 48 MHzUp to Three MMC, SD, SDIO Ports1-, 4- and 8-Bit MMC, SD, SDIO ModesMMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V OperationUp to 48-MHz Data Transfer RateSupports Card Detect and Write ProtectComplies With MMC4.3, SD, SDIO 2.0 SpecificationsUp to Three I2C Master and Slave InterfacesStandard Mode (up to 100 kHz)Fast Mode (up to 400 kHz)Up to Four Banks of General-Purpose I/O (GPIO) Pins32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)Up to Three External DMA Event Inputs that can Also be Used as Interrupt InputsEight 32-Bit General-Purpose TimersDMTIMER1 is a 1-ms Timer Used for Operating System (OS) TicksDMTIMER4–DMTIMER7 are Pinned OutOne Watchdog TimerSGX530 3D Graphics EngineTile-Based Architecture Delivering up to 20 Million Polygons per SecondUniversal Scalable Shader Engine (USSE) is a Multithreaded Engine Incorporating Pixel and Vertex Shader FunctionalityAdvanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0, and OpenMaxFine-Grained Task Switching, Load Balancing, and Power ManagementAdvanced Geometry DMA-Driven Operation for Minimum CPU InteractionProgrammable High-Quality Image Anti-AliasingFully Virtualized Memory Addressing for OS Operation in a Unified Memory ArchitectureLCD ControllerUp to 24-Bit Data Output; 8 Bits per Pixel (RGB)Resolution up to 2048 × 2048 (With Maximum 126-MHz Pixel Clock)Integrated LCD Interface Display Driver (LIDD) ControllerIntegrated Raster ControllerIntegrated DMA Engine to Pull Data from the External Frame Buffer Without Burdening the Processor via Interrupts or a Firmware Timer512-Word Deep Internal FIFOSupported Display Types:Character Displays - Uses LIDD Controller to Program these DisplaysPassive Matrix LCD Displays - Uses LCD Raster Display Controller to Provide Timing and Data for Constant Graphics Refresh to a Passive DisplayActive Matrix LCD Displays - Uses External Frame Buffer Space and the Internal DMA Engine to Drive Streaming Data to the Panel12-Bit Successive Approximation Register (SAR) ADC200K Samples per SecondInput can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog SwitchCan be Configured to Operate as a 4-Wire, 5-Wire, or 8-Wire Resistive Touch Screen Controller (TSC) InterfaceUp to Three 32-Bit eCAP ModulesConfigurable as Three Capture Inputs or Three Auxiliary PWM OutputsUp to Three Enhanced High-Resolution PWM Modules (eHRPWMs)Dedicated 16-Bit Time-Base Counter With Time and Frequency ControlsConfigurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric OutputsUp to Three 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) ModulesDevice IdentificationContains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory ProgrammableProduction IDDevice Part Number (Unique JTAG ID)Device Revision (Readable by Host ARM)Debug Interface SupportJTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS DebugSupports Device Boundary ScanSupports IEEE 1500DMAOn-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:Transfers to and from On-Chip MemoriesTransfers to and from External Storage (EMIF, GPMC, Slave Peripherals)Inter-Processor Communication (IPC)Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSSMailbox Registers that Generate InterruptsFour Initiators (Cortex-A8, PRCM, PRU0, PRU1)Spinlock has 128 Software-Assigned Lock RegistersSecurityCrypto Hardware Accelerators (AES, SHA, RNG)Secure Boot (optional; requires custom part engagement with TI)Boot ModesBoot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input PinPackages:298-Pin S-PBGA-N298 Via Channel Package(ZCE Suffix), 0.65-mm Ball Pitch324-Pin S-PBGA-N324 Package(ZCZ Suffix), 0.80-mm Ball Pitch
Description
AI
The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image, graphics processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS. The devices support high-level operating systems (HLOS). Processor SDK Linux®and TI-RTOS are available free of charge from TI.
The AM335x microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:
The contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:
The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.
The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.
The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image, graphics processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS. The devices support high-level operating systems (HLOS). Processor SDK Linux®and TI-RTOS are available free of charge from TI.
The AM335x microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:
The contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:
The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.
The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.