Catalog(1 parts)
| Part | Clock Frequency▲▼ | Trigger Type | Supplier Device Package | Number of Bits per Element▲▼ | Mounting Type | Current - Quiescent (Iq)▲▼ | Output Type | Max Propagation Delay @ V, Max CL▲▼ | Current - Output High, Low▲▼ | Current - Output High, Low▲▼ | Type | Operating Temperature▲▼ | Operating Temperature▲▼ | Package / Case | Number of Elements▲▼ | Voltage - Supply▲▼ | Voltage - Supply▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments SN74F175NSRFlip Flop 1 Element D-Type 4 Bit Positive Edge 16-SOIC (0.209", 5.30mm Width) | 140000000 Hz | Positive Edge | 16-SO | 4 ul | Surface Mount | 0.03400000184774399 A | Complementary | 8.499999815114734e-9 s | 0.019999999552965164 A | 0.0010000000474974513 A | D-Type | 70 °C | 0 °C | 16-SOIC (0.209", 5.30mm Width) | 1 ul | 5.5 V | 4.5 V |
Key Features
• Contains Four Flip-Flops With Double-Rail OutputsBuffered Clock and Direct Clear InputsApplications Include:Buffer/Storage RegistersShift RegistersPattern GeneratorsContains Four Flip-Flops With Double-Rail OutputsBuffered Clock and Direct Clear InputsApplications Include:Buffer/Storage RegistersShift RegistersPattern Generators
Description
AI
This positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic with a direct clear (CLR)\ input. Information at the data (D) inputs meeting setup-time requirements is transferred to outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
This positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic with a direct clear (CLR)\ input. Information at the data (D) inputs meeting setup-time requirements is transferred to outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.