74AUC1G79 Series

Single Positive-Edge-Triggered D-Type Flip-Flop

Catalog

Single Positive-Edge-Triggered D-Type Flip-Flop

Part	Number of Elements	Current - Quiescent (Iq)	Voltage - Supply (Minimum)	Voltage - Supply (Maximum)	Function	Clock Frequency	Trigger Type	Type	Number of Bits per Element	Max CL	Max Propagation Delay	Operating Temperature (Max)	Operating Temperature (Min)	Mounting Type	Current - Output High	Current - Output Low	Output Type	Package / Case	Package Name	Input Capacitance	Package Width	Package Length
Texas Instruments SN74AUC1G79DCKRG4	1	10 µA	0.8 V	2.7 V	Standard	275 MHz	Positive Edge	D-Type	1 bits	30 pF	1.8 ns	85 °C	-40 °C	Surface Mount	9 mA	9 mA	Non-Inverted	5-TSSOP SC-70-5 SOT-353	SC-70-5	2.5 pF
Texas Instruments SN74AUC1G79YZPR	1	10 µA	0.8 V	2.7 V	Standard	275 MHz	Positive Edge	D-Type	1 bits	30 pF	1.8 ns	85 °C	-40 °C	Surface Mount	9 mA	9 mA	Non-Inverted	5-XFBGA DSBGA	5-DSBGA	2.5 pF	0.9 mm	1.4 mm
Texas Instruments SN74AUC1G79YEPR	1	10 µA	0.8 V	2.7 V	Standard	275 MHz	Positive Edge	D-Type	1 bits	30 pF	1.8 ns	85 °C	-40 °C	Surface Mount	9 mA	9 mA	Non-Inverted	5-XFBGA DSBGA	5-DSBGA	2.5 pF	0.9 mm	1.4 mm
Texas Instruments SN74AUC1G79DCKR	1	10 µA	0.8 V	2.7 V	Standard	275 MHz	Positive Edge	D-Type	1 bits	30 pF	1.8 ns	85 °C	-40 °C	Surface Mount	9 mA	9 mA	Non-Inverted	5-TSSOP SC-70-5 SOT-353	SC-70-5	2.5 pF
Texas Instruments SN74AUC1G79YZAR	1	10 µA	0.8 V	2.7 V	Standard	275 MHz	Positive Edge	D-Type	1 bits	30 pF	1.8 ns	85 °C	-40 °C	Surface Mount	9 mA	9 mA	Non-Inverted	5-XFBGA DSBGA	5-DSBGA	2.5 pF	0.9 mm	1.4 mm
Texas Instruments SN74AUC1G79YEAR	1	10 µA	0.8 V	2.7 V	Standard	275 MHz	Positive Edge	D-Type	1 bits	30 pF	1.8 ns	85 °C	-40 °C	Surface Mount	9 mA	9 mA	Non-Inverted	5-XFBGA DSBGA	5-DSBGA	2.5 pF	0.9 mm	1.4 mm

Catalog

Single Positive-Edge-Triggered D-Type Flip-Flop

Description

This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCCoperation. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCCoperation. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.