Catalog(2 parts)
| Part | Type | Operating Temperature▲▼ | Operating Temperature▲▼ | Data Rate▲▼ | Receiver Hysteresis▲▼ | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Package / Case | Protocol | Number of Drivers/Receivers▲▼ | Number of Drivers/Receivers▲▼ | Mounting Type | Supplier Device Package |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Receiver | -40 °C | 85 °C | 262144000 bit/s | 0.02500000037252903 V | 3.5999999046325684 V | 3 V | 48-VFQFN Exposed Pad | LVDS, Multipoint | 0 ul | 4 ul | Surface Mount | 48-VQFN (7x7) | |
Receiver | -40 °C | 85 °C | 262144000 bit/s | 0.02500000037252903 V | 3.5999999046325684 V | 3 V | 48-VFQFN Exposed Pad | LVDS, Multipoint | 0 ul | 4 ul | Surface Mount | 48-VQFN (7x7) |
Key Features
• Low-voltage differential 30Ω to 55Ω line receivers for signaling rates(1)up to 250Mbps; Clock Frequencies up to 125MHzType-1 receiver incorporates 25mV of input threshold hysteresisType-2 receiver provides 100mV offset threshold to detect open-circuit and idle-bus conditionsWide receiver input common-mode voltage range, –1V to 3.4V, allows 2V of ground noiseMeets or exceeds the M-LVDS standard TIA/EIA-899 for multipoint topologyHigh input impedance when Vcc ≤ 1.5VEnhanced ESD Protection: 7kV HBM on all pins48-Pin 7 X 7 QFN (RGZ)(1)The signaling rate of a line is the number of voltage transitions that are made per second, expressed in the units bps (bits per second).Low-voltage differential 30Ω to 55Ω line receivers for signaling rates(1)up to 250Mbps; Clock Frequencies up to 125MHzType-1 receiver incorporates 25mV of input threshold hysteresisType-2 receiver provides 100mV offset threshold to detect open-circuit and idle-bus conditionsWide receiver input common-mode voltage range, –1V to 3.4V, allows 2V of ground noiseMeets or exceeds the M-LVDS standard TIA/EIA-899 for multipoint topologyHigh input impedance when Vcc ≤ 1.5VEnhanced ESD Protection: 7kV HBM on all pins48-Pin 7 X 7 QFN (RGZ)(1)The signaling rate of a line is the number of voltage transitions that are made per second, expressed in the units bps (bits per second).
Description
AI
The SN65MLVD048 is a quad-channel M-LVDS receiver. This device is designed in full compliance with the TIA/EIA-899 (M-LVDS) standard, which is optimized to operate at signaling rates up to 250Mbps. Each receiver channel is controlled by a receive enable ( RE). When RE = low, the corresponding channel is enabled; when RE = high, the corresponding channel is disabled.
The M-LVDS standard defines two types of receivers, designated as Type-1 and Type-2. Type-1 receivers have thresholds centered about zero with 25mV of hysteresis to prevent output oscillations with loss of input; Type-2 receivers implement a failsafe by using an offset threshold. Receiver outputs are slew rate controlled to reduce EMI and crosstalk effects associated with large current surges.
The devices are characterized for operation from –40°C to 85°C.
The SN65MLVD048 is a quad-channel M-LVDS receiver. This device is designed in full compliance with the TIA/EIA-899 (M-LVDS) standard, which is optimized to operate at signaling rates up to 250Mbps. Each receiver channel is controlled by a receive enable ( RE). When RE = low, the corresponding channel is enabled; when RE = high, the corresponding channel is disabled.
The M-LVDS standard defines two types of receivers, designated as Type-1 and Type-2. Type-1 receivers have thresholds centered about zero with 25mV of hysteresis to prevent output oscillations with loss of input; Type-2 receivers implement a failsafe by using an offset threshold. Receiver outputs are slew rate controlled to reduce EMI and crosstalk effects associated with large current surges.
The devices are characterized for operation from –40°C to 85°C.