Catalog(6 parts)
| Part | Logic Type | Supply Voltage▲▼ | Supply Voltage▲▼ | Operating Temperature▲▼ | Operating Temperature▲▼ | Mounting Type | Supplier Device Package | Package / Case▲▼ | Package / Case | Package / Case▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|
IEEE STD 1284 Translation Transceiver | 4.5 V | 5.5 V | 70 °C | 0 °C | Surface Mount | 20-SOIC | 0.007493000011891127 m, 0.007499999832361937 m | 20-SOIC | ||
IEEE STD 1284 Translation Transceiver | 4.5 V | 5.5 V | 70 °C | 0 °C | Surface Mount | 20-TSSOP | 0.004394200164824724 m | 20-TSSOP | 0.004399999976158142 m | |
IEEE STD 1284 Translation Transceiver | 4.5 V | 5.5 V | 70 °C | 0 °C | Surface Mount | 20-TSSOP | 0.004394200164824724 m | 20-TSSOP | 0.004399999976158142 m | |
IEEE STD 1284 Translation Transceiver | 4.5 V | 5.5 V | 70 °C | 0 °C | Surface Mount | 20-SSOP | 0.0052999998442828655 m, 0.005308600142598152 m | 20-SSOP | ||
IEEE STD 1284 Translation Transceiver | 4.5 V | 5.5 V | 70 °C | 0 °C | Surface Mount | 20-SOIC | 0.007493000011891127 m, 0.007499999832361937 m | 20-SOIC | ||
IEEE STD 1284 Translation Transceiver | 4.5 V | 5.5 V | 70 °C | 0 °C | Surface Mount | 20-TSSOP | 0.004394200164824724 m | 20-TSSOP | 0.004399999976158142 m |
Key Features
• 4.5-V to 5.5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 20 ns at 5 V3-State Outputs Directly Drive Bus LinesFlow-Through Architecture Optimizes PCB LayoutCenter-Pin VCCand GND Configurations Minimize High-Speed Switching NoiseESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)Designed for the IEEE 1284-I (Level-1 Type) and IEEE 1284-II (Level-2 Type) Electrical Specifications4.5-V to 5.5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 20 ns at 5 V3-State Outputs Directly Drive Bus LinesFlow-Through Architecture Optimizes PCB LayoutCenter-Pin VCCand GND Configurations Minimize High-Speed Switching NoiseESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)Designed for the IEEE 1284-I (Level-1 Type) and IEEE 1284-II (Level-2 Type) Electrical Specifications
Description
AI
The ’ACT1284 devices are designed for asynchronous two-way communication between data buses. The control function minimizes external timing requirements.
The devices allow data transmission in either the A-to-B or the B-to-A direction for bits 1, 2, 3, and 4, depending on the logic level at the direction-control (DIR) input. Bits 5, 6, and 7, however, always transmit in the A-to-B direction.
The output drive for each mode is determined by the high-drive (HD) control pin. When HD is high, the high drive is delivered by the totem-pole configuration, and when HD is low, the outputs are open drain. This meets the drive requirements as specified in the IEEE 1284-I (level-1 type) and the IEEE 1284-II (level-2 type) parallel peripheral-interface specification.
The ’ACT1284 devices are designed for asynchronous two-way communication between data buses. The control function minimizes external timing requirements.
The devices allow data transmission in either the A-to-B or the B-to-A direction for bits 1, 2, 3, and 4, depending on the logic level at the direction-control (DIR) input. Bits 5, 6, and 7, however, always transmit in the A-to-B direction.
The output drive for each mode is determined by the high-drive (HD) control pin. When HD is high, the high drive is delivered by the totem-pole configuration, and when HD is low, the outputs are open drain. This meets the drive requirements as specified in the IEEE 1284-I (level-1 type) and the IEEE 1284-II (level-2 type) parallel peripheral-interface specification.