Catalog(3 parts)
| Part | Max Propagation Delay @ V, Max CL▲▼ | Number of Bits per Element▲▼ | Mounting Type | Function | Output Type | Package / Case▲▼ | Package / Case▲▼ | Package / Case | Type | Supplier Device Package | Trigger Type | Current - Output High, Low▲▼ | Number of Elements▲▼ | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Input Capacitance▲▼ | Clock Frequency▲▼ | Operating Temperature▲▼ | Operating Temperature▲▼ | Package / Case▲▼ | Package / Case▲▼ | Package / Case▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments SN74ABT821ADWFlip Flop 1 Element D-Type 10 Bit Positive Edge 24-SOIC (0.295", 7.50mm Width) | 6.20000006890109e-9 s | 10 ul | Surface Mount | Standard | Tri-State, Non-Inverted | 0.007499999832361937 m | 0.007493000011891127 m | 24-SOIC | D-Type | 24-SOIC | Positive Edge | 0.03200000151991844 A, 0.06400000303983688 A | 1 ul | 5.5 V | 4.5 V | 3.4999999860146898e-12 F | 125000000 Hz | 85 °C | -40 °C | |||
Texas Instruments SN74ABT821ANTFlip Flop 1 Element D-Type 10 Bit Positive Edge 24-DIP (0.300", 7.62mm) | 6.20000006890109e-9 s | 10 ul | Through Hole | Standard | Tri-State, Non-Inverted | 24-DIP | D-Type | 24-PDIP | Positive Edge | 0.03200000151991844 A, 0.06400000303983688 A | 1 ul | 5.5 V | 4.5 V | 3.4999999860146898e-12 F | 125000000 Hz | 85 °C | -40 °C | 0.007619999814778566 m, 0.007619999814778566 m | ||||
Texas Instruments SN74ABT821ADBRFlip Flop 1 Element D-Type 10 Bit Positive Edge 24-SSOP (0.209", 5.30mm Width) | 6.20000006890109e-9 s | 10 ul | Surface Mount | Standard | Tri-State, Non-Inverted | 24-SSOP | D-Type | 24-SSOP | Positive Edge | 0.03200000151991844 A, 0.06400000303983688 A | 1 ul | 5.5 V | 4.5 V | 3.4999999860146898e-12 F | 125000000 Hz | 85 °C | -40 °C | 0.005308600142598152 m | 0.0052999998442828655 m |
Key Features
• State-of-the-ArtEPIC-IIBTMBiCMOS Design Significantly Reduces Power DissipationESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17Typical VOLP(Output Ground Bounce) < 1 V at VCC= 5 V, TA= 25°CHigh-Impedance State During Power Up and Power DownHigh-Drive Outputs (-32-mA IOH, 64-mA IOL)Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPsEPIC-IIB is a trademark of Texas Instruments Incorporated.State-of-the-ArtEPIC-IIBTMBiCMOS Design Significantly Reduces Power DissipationESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17Typical VOLP(Output Ground Bounce) < 1 V at VCC= 5 V, TA= 25°CHigh-Impedance State During Power Up and Power DownHigh-Drive Outputs (-32-mA IOH, 64-mA IOL)Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPsEPIC-IIB is a trademark of Texas Instruments Incorporated.
Description
AI
These 10-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.
The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the devices provide true data at the Q outputs.
A buffered output-enable (OE\) input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.
When VCCis between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT821 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT821A is characterized for operation from -40°C to 85°C.
These 10-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.
The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the devices provide true data at the Q outputs.
A buffered output-enable (OE\) input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.
When VCCis between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT821 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT821A is characterized for operation from -40°C to 85°C.