Catalog
1.2-V to 1.8-V clock buffer and level translator
Description
AI
The CDCBT1001 is a 1.2-V to 1.8-V clock buffer and level translator. The VDD_IN pin supply voltage defines the input LVCMOS clock level. The VDD_OUT pin supply voltage defines the output LVCMOS clock level. VDD_IN = 1.2 V ± 10%. VDD_OUT = 1.8 V ± 10%
The 12-kHz to 5-MHz additive RMS jitter at 24 MHz is less than 0.8 ps.
The CDCBT1001 is a 1.2-V to 1.8-V clock buffer and level translator. The VDD_IN pin supply voltage defines the input LVCMOS clock level. The VDD_OUT pin supply voltage defines the output LVCMOS clock level. VDD_IN = 1.2 V ± 10%. VDD_OUT = 1.8 V ± 10%
The 12-kHz to 5-MHz additive RMS jitter at 24 MHz is less than 0.8 ps.