Catalog(1 parts)
| Part | Supplier Device Package | Current - Output High, Low▲▼ | Current - Output High, Low▲▼ | Output Function | Output | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Max Propagation Delay @ V, Max CL▲▼ | Number of Bits▲▼ | Package / Case | Package / Case▲▼ | Type | Operating Temperature▲▼ | Operating Temperature▲▼ | Mounting Type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
16-SOIC | 0.019999999552965164 A | 0.0010000000474974513 A | A<B, A=B, A>B | Active High | 4.75 V | 5.25 V | 1.7999999712969842e-8 s | 4 ul | 16-SOIC | 0.003911599982529879 m, 3.900000095367432 ul | Magnitude Comparator | 70 °C | 0 °C | Surface Mount |
Description
AI
These four-bit magnitude comparators perform comparison of straight binary and straight BCD (8-4-2-1) codes. Three fully decoded decisions about two 4-bit words (A, B) are made and are externally available at three outputs. These devices are fully expandable to any number of bits without external gates. Words of greater length may be compared by connecting comparators in cascade. The A > B, A < B, and A = B outputs of a stage handling less-significant bits are connected to the corresponding A > B, A < B, and A = B inputs of the next stage handling more-significant bits. The stage handling the least-significant bits must have a high-level voltage applied to the A = B input. The cascading paths of the '85, 'LS85, and 'S85 are implemented with only a two-gate-level delay to reduce overall comparison times for long words. An alternate method of cascading which further reduces the comparison time is shown in the typical application data.
These four-bit magnitude comparators perform comparison of straight binary and straight BCD (8-4-2-1) codes. Three fully decoded decisions about two 4-bit words (A, B) are made and are externally available at three outputs. These devices are fully expandable to any number of bits without external gates. Words of greater length may be compared by connecting comparators in cascade. The A > B, A < B, and A = B outputs of a stage handling less-significant bits are connected to the corresponding A > B, A < B, and A = B inputs of the next stage handling more-significant bits. The stage handling the least-significant bits must have a high-level voltage applied to the A = B input. The cascading paths of the '85, 'LS85, and 'S85 are implemented with only a two-gate-level delay to reduce overall comparison times for long words. An alternate method of cascading which further reduces the comparison time is shown in the typical application data.