74LVC1G74 Series
Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset
Manufacturer: Texas Instruments
Catalog(3 parts)
| Part | Output Type | Current - Quiescent (Iq)▲▼ | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Clock Frequency▲▼ | Operating Temperature▲▼ | Operating Temperature▲▼ | Type | Number of Bits per Element▲▼ | Trigger Type | Number of Elements▲▼ | Mounting Type | Current - Output High, Low▲▼ | Current - Output High, Low▲▼ | Max Propagation Delay @ V, Max CL▲▼ | Function | Input Capacitance▲▼ | Supplier Device Package | Package / Case | Package / Case▲▼ | Package / Case▲▼ | Max Propagation Delay @ V, Max CL▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Complementary | 0.000009999999747378752 A | 5.5 V | 1.649999976158142 V | 200000000 Hz | -40 °C | 125 °C | D-Type | 1 ul | Positive Edge | 1 ul | Surface Mount | 0.03200000151991844 A | 0.03200000151991844 A | 4.399999919968422e-9 s | Reset, Set(Preset) | 4.999999980020986e-12 F | 8-X2SON (1.4x1) | 8-XFDFN | ||||
Texas Instruments SN74LVC1G74DCUTFlip Flop 1 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091", 2.30mm Width) | Complementary | 0.000009999999747378752 A | 5.5 V | 1.649999976158142 V | 200000000 Hz | -40 °C | 125 °C | D-Type | 1 ul | Positive Edge | 1 ul | Surface Mount | 0.03200000151991844 A | 0.03200000151991844 A | 4.399999919968422e-9 s | Reset, Set(Preset) | 4.999999980020986e-12 F | 8-VFSOP | 0.002311399905011058 m | 0.002300000051036477 m | ||
Texas Instruments SN74LVC1G74DCURFlip Flop 1 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091", 2.30mm Width) | Complementary | 0.000009999999747378752 A | 5.5 V | 1.649999976158142 V | 200000000 Hz | -40 °C | 125 °C | D-Type | 1 ul | Positive Edge | 1 ul | Surface Mount | 0.03200000151991844 A | 0.03200000151991844 A | Reset, Set(Preset) | 4.999999980020986e-12 F | 8-VFSOP | 0.002311399905011058 m | 0.002300000051036477 m | 6.4000000854491645e-9 s |
Key Features
• Available in the Texas Instruments NanoFree™ packageSupports 5-V VCCoperationInputs accept voltages to 5.5-VSupports down translation to VCCMaximum tpdof 5.9-ns at 3.3-VLow power consumption, 10-µA maximum ICC±24-mA output drive at 3.3-VTypical VOLP(output ground bounce) < 0.8-V at VCC= 3.3-V, TA= 25°CTypical VOHV(output VOHundershoot) > 2-V at VCC= 3.3 V, TA= 25°CIoffsupports live insertion, partial-power-down mode, and back-drive protectionLatch-up performance exceeds 100 mA per JESD 78, class IIESD protection exceeds JESD 222000-V human-body model200-V machine model1000-V charged-device modelAvailable in the Texas Instruments NanoFree™ packageSupports 5-V VCCoperationInputs accept voltages to 5.5-VSupports down translation to VCCMaximum tpdof 5.9-ns at 3.3-VLow power consumption, 10-µA maximum ICC±24-mA output drive at 3.3-VTypical VOLP(output ground bounce) < 0.8-V at VCC= 3.3-V, TA= 25°CTypical VOHV(output VOHundershoot) > 2-V at VCC= 3.3 V, TA= 25°CIoffsupports live insertion, partial-power-down mode, and back-drive protectionLatch-up performance exceeds 100 mA per JESD 78, class IIESD protection exceeds JESD 222000-V human-body model200-V machine model1000-V charged-device model
Description
AI
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.