ADS54J60 Series

Dual-Channel, 16-Bit, 1.0-GSPS Analog-to-Digital Converter (ADC)

Catalog

Dual-Channel, 16-Bit, 1.0-GSPS Analog-to-Digital Converter (ADC)

Part	Architecture	Data Interface	Reference Type	Number of A/D Converters	Supplier Device Package	Features	Number of Inputs	Sampling Rate (Per Second)	Package / Case	Voltage - Supply, Analog [Max]	Voltage - Supply, Analog [Min]	Input Type	Operating Temperature [Max]	Operating Temperature [Min]	Voltage - Supply, Digital [Min]	Voltage - Supply, Digital [Max]	Ratio - S/H:ADC	Mounting Type	Configuration	Number of Bits
Texas Instruments ADS54J60IRMP	Pipelined	JESD204B	External	2	72-VQFN (10x10)	Simultaneous Sampling	2	1 G	72-VFQFN Exposed Pad	2 V, 3.6 V	1.8 V, 2.85 V	Differential	85 °C	-40 °C	1.7 V	2 V	1:1	Surface Mount	S/H-ADC	16

Catalog

Dual-Channel, 16-Bit, 1.0-GSPS Analog-to-Digital Converter (ADC)

Key Features

• 16-bit resolution, dual-channel, 1-GSPS ADCNoise floor: –159 dBFS/HzSpectral performance (fIN= 170 MHz at –1 dBFS):SNR: 70 dBFSNSD: –157 dBFS/HzSFDR: 86 dBc (including interleaving tones)SFDR: 89 dBc (except HD2, HD3, and interleaving tones)Spectral performance (fIN= 350 MHz at –1 dBFS):SNR: 67.5 dBFSNSD: –154.5 dBFS/HzSFDR: 75 dBcSFDR: 85 dBc (except HD2, HD3, and interleaving tones)Channel isolation: 100 dBc at fIN= 170 MHzInput full-scale: 1.9 VPPInput bandwidth (3 dB): 1.2 GHzOn-chip ditherIntegrated wideband DDC blockJESD204B interface with subclass 1 support:2 lanes per ADC at 10.0 Gbps4 lanes per ADC at 5.0 GbpsSupport for multi-chip synchronizationPower dissipation: 1.35 W/Ch at 1 GSPSPackage: 72-pin VQFNP (10 mm × 10 mm)16-bit resolution, dual-channel, 1-GSPS ADCNoise floor: –159 dBFS/HzSpectral performance (fIN= 170 MHz at –1 dBFS):SNR: 70 dBFSNSD: –157 dBFS/HzSFDR: 86 dBc (including interleaving tones)SFDR: 89 dBc (except HD2, HD3, and interleaving tones)Spectral performance (fIN= 350 MHz at –1 dBFS):SNR: 67.5 dBFSNSD: –154.5 dBFS/HzSFDR: 75 dBcSFDR: 85 dBc (except HD2, HD3, and interleaving tones)Channel isolation: 100 dBc at fIN= 170 MHzInput full-scale: 1.9 VPPInput bandwidth (3 dB): 1.2 GHzOn-chip ditherIntegrated wideband DDC blockJESD204B interface with subclass 1 support:2 lanes per ADC at 10.0 Gbps4 lanes per ADC at 5.0 GbpsSupport for multi-chip synchronizationPower dissipation: 1.35 W/Ch at 1 GSPSPackage: 72-pin VQFNP (10 mm × 10 mm)

Description

The ADS54J60 is a low-power, wide-bandwidth, 16-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J60 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 16-bit data from each channel. The ADS54J60 is a low-power, wide-bandwidth, 16-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J60 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 16-bit data from each channel.