ADC08D502 Series
Dual-Channel, 8-Bit, 500-MSPS Analog-to-Digital Converter (ADC)
Manufacturer: Texas Instruments
Catalog(1 parts)
| Part | Voltage - Supply, Analog▲▼ | Voltage - Supply, Analog▲▼ | Reference Type | Number of Inputs▲▼ | Architecture | Ratio - S/H:ADC | Voltage - Supply, Digital▲▼ | Voltage - Supply, Digital▲▼ | Configuration | Data Interface | Number of A/D Converters▲▼ | Mounting Type | Operating Temperature▲▼ | Operating Temperature▲▼ | Sampling Rate (Per Second)▲▼ | Supplier Device Package | Features | Input Type | Number of Bits▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments ADC08D502CIYB/NOPB8 Bit Analog to Digital Converter 2 Input 2 Folding Interpolating 128-HLQFP (20x20) | 1.7999999523162842 V | 2 V | Internal | 2 ul | Folding Interpolating | 1:1 | 1.7999999523162842 V | 2 V | MUX-S/H-ADC | LVDS - Parallel | 2 ul | Surface Mount | -40 °C | 85 °C | 500 m | 128-HLQFP (20x20) | Simultaneous Sampling | Differential | 8 ul |
Key Features
• Internal Sample-and-HoldSingle +1.9V ±0.1V OperationChoice of SDR or DDR Output ClockingMultiple ADC Synchronization CapabilitySpecified No Missing CodesSerial Interface for Extended ControlFine Adjustment of Input Full-Scale Range and OffsetDuty Cycle Corrected Sample ClockKey SpecificationsResolution: 8 BitsMax Conversion Rate: 500 MSPS (min)Bit Error Rate: 10-18(typ)ENOB @ 250 MHz Input: 7.5 Bits (typ)DNL: ±0.15 LSB (typ)Power ConsumptionOperating: 1.4 W (typ)Power Down Mode: 3.5 mW (typ)All trademarks are the property of their respective owners.Internal Sample-and-HoldSingle +1.9V ±0.1V OperationChoice of SDR or DDR Output ClockingMultiple ADC Synchronization CapabilitySpecified No Missing CodesSerial Interface for Extended ControlFine Adjustment of Input Full-Scale Range and OffsetDuty Cycle Corrected Sample ClockKey SpecificationsResolution: 8 BitsMax Conversion Rate: 500 MSPS (min)Bit Error Rate: 10-18(typ)ENOB @ 250 MHz Input: 7.5 Bits (typ)DNL: ±0.15 LSB (typ)Power ConsumptionOperating: 1.4 W (typ)Power Down Mode: 3.5 mW (typ)All trademarks are the property of their respective owners.
Description
AI
The ADC08D502 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 500 MSPS. Consuming a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt supply, this device is specified to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input signal and a 500 MHz sample rate while providing a 10-18B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.
Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate.
The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA≤ +85°C) temperature range.
The ADC08D502 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 500 MSPS. Consuming a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt supply, this device is specified to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input signal and a 500 MHz sample rate while providing a 10-18B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.
Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate.
The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA≤ +85°C) temperature range.