Catalog(6 parts)
| Part | Mounting Type | Package / Case▲▼ | Package / Case▲▼ | Package / Case | Supplier Device Package | Operating Temperature▲▼ | Operating Temperature▲▼ | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Number of Bits per Element▲▼ | Current - Output High, Low▲▼ | Current - Output High, Low▲▼ | Number of Elements▲▼ | Output Type | Package / Case▲▼ | Package / Case▲▼ | Package / Case▲▼ | Package / Case▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments SN74LVC543ADWG4Transceiver, Non-Inverting 1 Element 8 Bit per Element 3-State Output 24-SOIC | Surface Mount | 0.007499999832361937 m | 0.007493000011891127 m | 24-SOIC | 24-SOIC | 85 °C | -40 °C | 3.5999999046325684 V | 1.649999976158142 V | 8 ul | 0.024000000208616257 A | 0.024000000208616257 A | 1 ul | 3-State | ||||
Texas Instruments SN74LVC543ADBRTransceiver, Non-Inverting 1 Element 8 Bit per Element 3-State Output 24-SSOP | Surface Mount | 24-SSOP | 24-SSOP | 85 °C | -40 °C | 3.5999999046325684 V | 1.649999976158142 V | 8 ul | 0.024000000208616257 A | 0.024000000208616257 A | 1 ul | 3-State | 0.005308600142598152 m | 0.0052999998442828655 m | ||||
Texas Instruments SN74LVC543APWTTransceiver, Non-Inverting 1 Element 8 Bit per Element 3-State Output 24-TSSOP | Surface Mount | 24-TSSOP | 24-TSSOP | 85 °C | -40 °C | 3.5999999046325684 V | 1.649999976158142 V | 8 ul | 0.024000000208616257 A | 0.024000000208616257 A | 1 ul | 3-State | 0.004399999976158142 m | 0.004394200164824724 m | ||||
Texas Instruments SN74LVC543ADWTransceiver, Non-Inverting 1 Element 8 Bit per Element 3-State Output 24-SOIC | Surface Mount | 0.007499999832361937 m | 0.007493000011891127 m | 24-SOIC | 24-SOIC | 85 °C | -40 °C | 3.5999999046325684 V | 1.649999976158142 V | 8 ul | 0.024000000208616257 A | 0.024000000208616257 A | 1 ul | 3-State | ||||
Texas Instruments SN74LVC543APWRTransceiver, Non-Inverting 1 Element 8 Bit per Element 3-State Output 24-TSSOP | Surface Mount | 24-TSSOP | 24-TSSOP | 85 °C | -40 °C | 3.5999999046325684 V | 1.649999976158142 V | 8 ul | 0.024000000208616257 A | 0.024000000208616257 A | 1 ul | 3-State | 0.004399999976158142 m | 0.004394200164824724 m | ||||
Texas Instruments SN74LVC543APWRE4Transceiver, Non-Inverting 1 Element 8 Bit per Element 3-State Output 24-TSSOP | Surface Mount | 24-TSSOP | 24-TSSOP | 85 °C | -40 °C | 3.5999999046325684 V | 1.649999976158142 V | 8 ul | 0.024000000208616257 A | 0.024000000208616257 A | 1 ul | 3-State | 0.004399999976158142 m | 0.004394200164824724 m |
Key Features
• Operates From 1.65 V to 3.6 VInputs Accept Voltages to 5.5 VMax tpdof 7 ns at 3.3 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2 V at VCC= 3.3 V, TA= 25°CSupports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)IoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 250 mA Per JESD 17Operates From 1.65 V to 3.6 VInputs Accept Voltages to 5.5 VMax tpdof 7 ns at 3.3 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2 V at VCC= 3.3 V, TA= 25°CSupports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)IoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 250 mA Per JESD 17
Description
AI
This octal registered transceiver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74LVC543A contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB\ or LEBA\) and output-enable (OEAB\ or OEBA\) inputs are provided for each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB)\ input must be low to enter data from A or to output data from B. If CEAB\ is low and LEAB\ is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB\ places the A latches in the storage mode. With CEAB\ and OEAB\ both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow for B to A is similar to that of A to B, but uses CEBA\, LEBA\, and OEBA\.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
This octal registered transceiver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74LVC543A contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB\ or LEBA\) and output-enable (OEAB\ or OEBA\) inputs are provided for each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB)\ input must be low to enter data from A or to output data from B. If CEAB\ is low and LEAB\ is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB\ places the A latches in the storage mode. With CEAB\ and OEAB\ both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow for B to A is similar to that of A to B, but uses CEBA\, LEBA\, and OEBA\.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.