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74ACT16245 Series

Enhanced product 16-ch, 4.5-V to 5.5-V inverters with Schmitt-Trigger inputs

Manufacturer: Texas Instruments

Catalog(4 parts)

PartOperating Temperature▲▼Operating Temperature▲▼Current - Output High, Low▲▼Current - Output High, Low▲▼Output TypeVoltage - Supply▲▼Voltage - Supply▲▼Number of Bits per Element▲▼Package / CaseMounting TypeNumber of Elements▲▼Supplier Device PackagePackage / Case▲▼Package / Case▲▼Current - Output High, Low▲▼Current - Output High, Low▲▼
Texas Instruments
74ACT16245DL
Transceiver, Non-Inverting 2 Element 8 Bit per Element 3-State Output 48-SSOP
85 °C
-40 °C
0.024000000208616257 A
0.024000000208616257 A
3-State
5.5 V
4.5 V
8 ul
48-BSSOP (0.295", 7.50mm Width)
Surface Mount
2 ul
48-SSOP
Texas Instruments
74ACT16245DLR
Transceiver, Non-Inverting 2 Element 8 Bit per Element 3-State Output 48-SSOP
85 °C
-40 °C
0.024000000208616257 A
0.024000000208616257 A
3-State
5.5 V
4.5 V
8 ul
48-BSSOP (0.295", 7.50mm Width)
Surface Mount
2 ul
48-SSOP
Texas Instruments
74ACT16245DGGR
Transceiver, Non-Inverting 2 Element 8 Bit per Element 3-State Output 48-TSSOP
85 °C
-40 °C
0.024000000208616257 A
0.024000000208616257 A
3-State
5.5 V
4.5 V
8 ul
48-TFSOP
Surface Mount
2 ul
48-TSSOP
0.006099999882280827 m
0.006095999851822853 m
Texas Instruments
SN74ACT16245QDLREP
Transceiver, Non-Inverting 2 Element 8 Bit per Element 3-State Output 48-SSOP
125 °C
-40 °C
3-State
5.5 V
4.5 V
8 ul
48-BSSOP (0.295", 7.50mm Width)
Surface Mount
2 ul
48-SSOP
0.01600000075995922 A
0.01600000075995922 A

Key Features

• Controlled BaselineOne Assembly/Test Site, One Fabrication SiteExtended Temperature Performance of –40°C to 125°CEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product Change NotificationQualification PedigreeMember of the Texas Instruments Widebus™ FamilyInputs Are TTL-Voltage Compatible3-State Outputs Drive Bus Lines DirectlyFlow-Through Architecture Optimizes PCB LayoutDistributed VCCand GND Pins Minimize High-Speed Switching NoiseComponent qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, highly accelerated stress test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life.Widebus is a trademark of Texas Instruments.Controlled BaselineOne Assembly/Test Site, One Fabrication SiteExtended Temperature Performance of –40°C to 125°CEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product Change NotificationQualification PedigreeMember of the Texas Instruments Widebus™ FamilyInputs Are TTL-Voltage Compatible3-State Outputs Drive Bus Lines DirectlyFlow-Through Architecture Optimizes PCB LayoutDistributed VCCand GND Pins Minimize High-Speed Switching NoiseComponent qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, highly accelerated stress test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life.Widebus is a trademark of Texas Instruments.

Description

AI
The SN74ACT16245Q-EP is a 16-bit bus transceiver organized as dual-octal noninverting 3-state transceivers and designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. The device allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The enable (G)\ input can be used to disable the devices so that the buses are effectively isolated. The SN74ACT16245Q-EP is a 16-bit bus transceiver organized as dual-octal noninverting 3-state transceivers and designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. The device allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The enable (G)\ input can be used to disable the devices so that the buses are effectively isolated.