Catalog(1 parts)
| Part | Input Type | Supplier Device Package | Package / Case | Sampling Rate (Per Second)▲▼ | Ratio - S/H:ADC | Reference Type | Number of A/D Converters▲▼ | Architecture | Configuration | Voltage - Supply, Analog▲▼ | Voltage - Supply, Analog▲▼ | Operating Temperature▲▼ | Operating Temperature▲▼ | Voltage - Supply, Digital▲▼ | Voltage - Supply, Digital▲▼ | Number of Bits▲▼ | Mounting Type | Number of Inputs▲▼ | Data Interface |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments ADC16V130CISQ/NOPB16 Bit Analog to Digital Converter 1 Input 1 Pipelined 64-WQFN (9x9) | Differential | 64-WQFN (9x9) | 64-WFQFN Exposed Pad | 130 m | 1:1 | External, Internal | 1 ul | Pipelined | S/H-ADC | 1.7000000476837158 V | 3.5999999046325684 V | -40 °C | 85 °C | 1.7000000476837158 V | 1.899999976158142 V | 16 b | Surface Mount | 1 ul | LVDS - Parallel |
Key Features
• Dual Supplies: 1.8V and 3.0V OperationOn Chip Automatic Calibration During Power-UpLow Power ConsumptionMulti-Level Multi-Function Pins for CLK/DF and PDPower-Down and Sleep ModesOn Chip Precision Reference and Sample-and-Hold CircuitOn Chip Low Jitter Duty-Cycle StabilizerOffset Binary or 2's Complement Data FormatFull Data Rate LVDS Output Port64-pin WQFN Package (9x9x0.8, 0.5mm Pin-Pitch)Key SpecificationsHigh IF Sampling ReceiversMulti-carrier Base Station ReceiversGSM/EDGE, CDMA2000, UMTS, LTE, and WiMaxTest and Measurement EquipmentCommunications InstrumentationData AcquisitionPortable InstrumentationAll trademarks are the property of their respective owners.Dual Supplies: 1.8V and 3.0V OperationOn Chip Automatic Calibration During Power-UpLow Power ConsumptionMulti-Level Multi-Function Pins for CLK/DF and PDPower-Down and Sleep ModesOn Chip Precision Reference and Sample-and-Hold CircuitOn Chip Low Jitter Duty-Cycle StabilizerOffset Binary or 2's Complement Data FormatFull Data Rate LVDS Output Port64-pin WQFN Package (9x9x0.8, 0.5mm Pin-Pitch)Key SpecificationsHigh IF Sampling ReceiversMulti-carrier Base Station ReceiversGSM/EDGE, CDMA2000, UMTS, LTE, and WiMaxTest and Measurement EquipmentCommunications InstrumentationData AcquisitionPortable InstrumentationAll trademarks are the property of their respective owners.
Description
AI
The ADC16V130 is a monolithic high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to 130 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and external component count while providing excellent dynamic performance. Automatic power-up calibration enables excellent dynamic performance and reduces part-to-part variation, and the ADC16V130 could be re-calibrated at any time by asserting and then de-asserting power-down. An integrated low noise and stable voltage reference and differential reference buffer amplifier easies board level design. On-chip duty cycle stabilizer with low additive jitter allows wide duty cycle range of input clock without compromising its dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.4 GHz. The digital data is provided via full data rate LVDS outputs – making possible the 64-pin, 9mm x 9mm WQFN package. The ADC16V130 operates on dual power supplies +1.8V and +3.0V with a power-down feature to reduce the power consumption to very low levels while allowing fast recovery to full operation.
The ADC16V130 is a monolithic high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to 130 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and external component count while providing excellent dynamic performance. Automatic power-up calibration enables excellent dynamic performance and reduces part-to-part variation, and the ADC16V130 could be re-calibrated at any time by asserting and then de-asserting power-down. An integrated low noise and stable voltage reference and differential reference buffer amplifier easies board level design. On-chip duty cycle stabilizer with low additive jitter allows wide duty cycle range of input clock without compromising its dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.4 GHz. The digital data is provided via full data rate LVDS outputs – making possible the 64-pin, 9mm x 9mm WQFN package. The ADC16V130 operates on dual power supplies +1.8V and +3.0V with a power-down feature to reduce the power consumption to very low levels while allowing fast recovery to full operation.