Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset
Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset
Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset
| Part | Max Propagation Delay | Max CL | Current - Quiescent (Iq) | Current - Output Low | Current - Output High | Output Type | Mounting Type | Trigger Type | Package Length | Package Name | Package Width | Type | Number of Elements | Number of Bits per Element | Input Capacitance | Function | Clock Frequency | Voltage - Supply (Maximum) | Voltage - Supply (Minimum) | Operating Temperature (Max) | Operating Temperature (Min) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
 Texas Instruments | 10 ns | 50 pF | 4 µA | 24 mA | 24 mA | Complementary | Through Hole | Positive Edge | 0.3 in | 14-CDIP | 7.62 mm | D-Type | 2 | 1 bits | 10 pF | Set(Preset) and Reset | 110 MHz | 5.5 V | 1.5 V | 125 °C | -55 °C |