74ALVCH373 Series

Octal Transparent D-Type Latch with 3-State Outputs

Catalog(5 parts)

Part	Circuit	Output Type	Supplier Device Package	Voltage - Supply▲▼	Voltage - Supply▲▼	Mounting Type	Independent Circuits▲▼	Current - Output High, Low▲▼	Current - Output High, Low▲▼	Operating Temperature▲▼	Operating Temperature▲▼	Package / Case	Package / Case▲▼	Package / Case▲▼	Delay Time - Propagation▲▼	Logic Type	Package / Case▲▼
Texas Instruments SN74ALVCH373DGVR D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-TVSOP	8:8	Tri-State	20-TVSOP	3.5999999046325684 V	1.649999976158142 V	Surface Mount	1 ul	0.024000000208616257 A	0.024000000208616257 A	-40 °C	85 °C	20-TFSOP	0.004399999976158142 m	0.004394200164824724 m	9.999999717180683e-10 s	D-Type Transparent Latch
Texas Instruments SN74ALVCH373PWR D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-TSSOP	8:8	Tri-State	20-TSSOP	3.5999999046325684 V	1.649999976158142 V	Surface Mount	1 ul	0.024000000208616257 A	0.024000000208616257 A	-40 °C	85 °C	20-TSSOP		0.004399999976158142 m	9.999999717180683e-10 s	D-Type Transparent Latch	0.004394200164824724 m
Texas Instruments SN74ALVCH373DW D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-SOIC	8:8	Tri-State	20-SOIC	3.5999999046325684 V	1.649999976158142 V	Surface Mount	1 ul	0.024000000208616257 A	0.024000000208616257 A	-40 °C	85 °C	20-SOIC			9.999999717180683e-10 s	D-Type Transparent Latch	0.007493000011891127 m, 0.007499999832361937 m
Texas Instruments SN74ALVCH373DWR D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-SOIC	8:8	Tri-State	20-SOIC	3.5999999046325684 V	1.649999976158142 V	Surface Mount	1 ul	0.024000000208616257 A	0.024000000208616257 A	-40 °C	85 °C	20-SOIC			9.999999717180683e-10 s	D-Type Transparent Latch	0.007493000011891127 m, 0.007499999832361937 m
Texas Instruments SN74ALVCH373GQNR D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-BGA MICROSTAR JUNIOR (4x3)	8:8	Tri-State	20-BGA MICROSTAR JUNIOR (4x3)	3.5999999046325684 V	1.649999976158142 V	Surface Mount	1 ul	0.024000000208616257 A	0.024000000208616257 A	-40 °C	85 °C	20-VFBGA			9.999999717180683e-10 s	D-Type Transparent Latch

Key Features

• Operates From 1.65 V to 3.6 VMax tpdof 3.3 ns at 3.3 V±24-mA Output Drive at 3.3 VBus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Operates From 1.65 V to 3.6 VMax tpdof 3.3 ns at 3.3 V±24-mA Output Drive at 3.3 VBus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)

Description

This octal transparent D-type latch is designed for 1.65-V to 3.6-V VCCoperation. The SN74ALVCH373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This octal transparent D-type latch is designed for 1.65-V to 3.6-V VCCoperation. The SN74ALVCH373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.