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74ABT162827 Series

20-ch, 4.5-V to 5.5-V buffers with TTL-compatible CMOS inputs and 3-state outputs

Manufacturer: Texas Instruments

Catalog(5 parts)

PartVoltage - Supply▲▼Voltage - Supply▲▼Current - Output High, Low▲▼Current - Output High, Low▲▼Number of Bits per Element▲▼Logic TypeNumber of Elements▲▼Supplier Device PackagePackage / Case▲▼Package / Case▲▼Package / CaseOperating Temperature▲▼Operating Temperature▲▼Output TypeMounting TypePackage / Case▲▼Package / Case▲▼
Texas Instruments
SN74ABT162827ADL
Buffer, Non-Inverting 2 Element 10 Bit per Element 3-State Output 56-SSOP
5.5 V
4.5 V
0.012000000104308128 A
0.012000000104308128 A
10 ul
Buffer, Non-Inverting
2 ul
56-SSOP
0.007493000011891127 m
0.007499999832361937 m
56-BSSOP
85 °C
-40 °C
3-State
Surface Mount
Texas Instruments
SN74ABT162827DL
Element Bit per Element Output
Texas Instruments
SN74ABT162827ADGGR
Buffer, Non-Inverting 2 Element 10 Bit per Element 3-State Output 56-TSSOP
5.5 V
4.5 V
0.012000000104308128 A
0.012000000104308128 A
10 ul
Buffer, Non-Inverting
2 ul
56-TSSOP
56-TFSOP
85 °C
-40 °C
3-State
Surface Mount
0.006099999882280827 m
0.006095999851822853 m
Texas Instruments
SN74ABT162827DLR
Element Bit per Element Output
Texas Instruments
SN74ABT162827DGGR
Element Bit per Element Output

Key Features

• Members of the Texas Instruments Widebus™ FamilyOutput Ports Have Equivalent 25-Series Resistors, So No External Resistors Are RequiredHigh-Impedance State During Power Up and Power DownTypical VOLP(Output Ground Bounce)< 1 V at VCC= 5 V, TA= 25°CDistributed VCCand GND Pin Minimizes High-Speed Switching NoiseIoffand Power-Up 3-State Support Hot InsertionFlow-Through Architecture Optimizes PCB LayoutLatch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)Widebus is a trademark of Texas Instruments.Members of the Texas Instruments Widebus™ FamilyOutput Ports Have Equivalent 25-Series Resistors, So No External Resistors Are RequiredHigh-Impedance State During Power Up and Power DownTypical VOLP(Output Ground Bounce)< 1 V at VCC= 5 V, TA= 25°CDistributed VCCand GND Pin Minimizes High-Speed Switching NoiseIoffand Power-Up 3-State Support Hot InsertionFlow-Through Architecture Optimizes PCB LayoutLatch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)Widebus is a trademark of Texas Instruments.

Description

AI
The ’ABT162827A devices are noninverting 20-bit buffers composed of two 10-bit buffers with separate output-enable signals. For either 10-bit buffer, the two output-enable (1OE1\ and 1OE2\, or 2OE1\ and 2OE2\) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer are in the high-impedance state. The outputs, which are designed to source or sink up to 12 mA, include equivalent 25-series resistors to reduce overshoot and undershoot. These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. To ensure the high-impedance state during power up or power down, OE\ shall be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The ’ABT162827A devices are noninverting 20-bit buffers composed of two 10-bit buffers with separate output-enable signals. For either 10-bit buffer, the two output-enable (1OE1\ and 1OE2\, or 2OE1\ and 2OE2\) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer are in the high-impedance state. The outputs, which are designed to source or sink up to 12 mA, include equivalent 25-series resistors to reduce overshoot and undershoot. These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. To ensure the high-impedance state during power up or power down, OE\ shall be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.