ADC32J25 Series
Dual-Channel, 12-Bit, 160-MSPS Analog-to-Digital Converter (ADC)
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
Dual-Channel, 12-Bit, 160-MSPS Analog-to-Digital Converter (ADC)
| Part | Mounting Type | Package / Case | Voltage - Supply, Analog [Min] | Voltage - Supply, Analog [Max] | Configuration | Supplier Device Package | Features | Sampling Rate (Per Second) | Voltage - Supply, Digital [Min] | Voltage - Supply, Digital [Max] | Number of A/D Converters | Operating Temperature [Min] | Operating Temperature [Max] | Number of Bits | Architecture | Reference Type | Number of Inputs | Input Type | Data Interface |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments ADC32J25IRGZT | Surface Mount | 48-VFQFN Exposed Pad | 1.7 V | 1.9 V | ADC | 48-VQFN (7x7) | Simultaneous Sampling | 160M | 1.7 V | 1.9 V | 2 | -40 °C | 85 °C | 12 | Pipelined | External, Internal | 2 | Differential | JESD204B |
Texas Instruments ADC32J25IRGZR | Surface Mount | 48-VFQFN Exposed Pad | 48-VQFN (7x7) |
Key Features
• Dual Channel12-Bit ResolutionSingle 1.8-V SupplyFlexible Input Clock Buffer with Divide-by-1, -2, -4SNR = 70.3 dBFS, SFDR = 88 dBc atfIN= 70 MHzUltralow Power Consumption:227 mW/Ch at 160 MSPSChannel Isolation: 105 dBInternal DitherJESD204B Serial Interface:Subclass 0, 1, 2 Compliant up to 3.2 GbpsSupports One Lane per ADC up to 160 MSPSSupport for Multichip SynchronizationPin-to-Pin Compatible with 14-Bit Version(ADC32J4X)Package: VQFN-48 (7 mm × 7 mm)Dual Channel12-Bit ResolutionSingle 1.8-V SupplyFlexible Input Clock Buffer with Divide-by-1, -2, -4SNR = 70.3 dBFS, SFDR = 88 dBc atfIN= 70 MHzUltralow Power Consumption:227 mW/Ch at 160 MSPSChannel Isolation: 105 dBInternal DitherJESD204B Serial Interface:Subclass 0, 1, 2 Compliant up to 3.2 GbpsSupports One Lane per ADC up to 160 MSPSSupport for Multichip SynchronizationPin-to-Pin Compatible with 14-Bit Version(ADC32J4X)Package: VQFN-48 (7 mm × 7 mm)
Description
AI
The ADC32J2x is a high-linearity, ultra-low power, dual-channel, 12-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The devices support JESD204B interfaces in order to reduce the number of interface lines, thus allowing for high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 12-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps.
The ADC32J2x is a high-linearity, ultra-low power, dual-channel, 12-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The devices support JESD204B interfaces in order to reduce the number of interface lines, thus allowing for high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 12-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps.