74HC7046 Series

High Speed CMOS Logic Phase-Locked Loop with VCO and Lock Detector

Catalog(3 parts)

Part	Package / Case	Package / Case▲▼	Mounting Type	Ratio - Input:Output▲▼	Ratio - Input:Output▲▼	Input	Number of Circuits▲▼	Type	Output	Supplier Device Package	Voltage - Supply▲▼	Voltage - Supply▲▼	Frequency - Max▲▼	Operating Temperature▲▼	Operating Temperature▲▼
Texas Instruments CD74HC7046AMT Phase Lock Loop (PLL) IC 38MHz 1 16-SOIC (0.154", 3.90mm Width)	16-SOIC	0.003911599982529879 m, 3.900000095367432 ul	Surface Mount	1 ul	2 ul	CMOS	1 ul	Phase Lock Loop (PLL)	CMOS	16-SOIC	2 V	6 V	38000000 Hz	-55 °C	125 °C
Texas Instruments CD74HC7046AE Phase Lock Loop (PLL) IC 38MHz 1 16-DIP (0.300", 7.62mm)	16-DIP	0.007619999814778566 m, 0.007619999814778566 m	Through Hole	1 ul	2 ul	CMOS	1 ul	Phase Lock Loop (PLL)	CMOS	16-PDIP	2 V	6 V	38000000 Hz	-55 °C	125 °C
Texas Instruments CD74HC7046AM Phase Lock Loop (PLL) IC 38MHz 1 16-SOIC (0.154", 3.90mm Width)	16-SOIC	0.003911599982529879 m, 3.900000095367432 ul	Surface Mount	1 ul	2 ul	CMOS	1 ul	Phase Lock Loop (PLL)	CMOS	16-SOIC	2 V	6 V	38000000 Hz	-55 °C	125 °C

Key Features

• Center Frequency of 18MHz (Typ) at VCC= 5V, Minimum Center Frequency of 12MHz at VCC= 4.5VChoice of Two Phase ComparatorsExclusive-OREdge-Triggered JK Flip-FlopExcellent VCO Frequency LinearityVCO-Inhibit Control for ON/OFF Keying and for Low Standby Power ConsumptionMinimal Frequency DriftZero Voltage Offset Due to Op-Amp BufferOperating Power-Supply Voltage RangeVCO Section...3V to 6VDigital Section...2V to 6VFanout (Over Temperature Range)Standard Outputs...10 LSTTL LoadsBus Driver Outputs...15 LSTTL LoadsWide Operating Temperature Range... –55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il≤ 1µA at VOL, VOHApplicationsFM Modulation and DemodulationFrequency Synthesis and MultiplicationFrequency DiscriminationTone DecodingData Synchronization and ConditioningVoltage-to-Frequency ConversionMotor-Speed ControlRelated LiteratureAN8823, CMOS Phase-Locked-Loop Application Using the CD74HC/HCT7046A and CD74HC/HCT7046ACenter Frequency of 18MHz (Typ) at VCC= 5V, Minimum Center Frequency of 12MHz at VCC= 4.5VChoice of Two Phase ComparatorsExclusive-OREdge-Triggered JK Flip-FlopExcellent VCO Frequency LinearityVCO-Inhibit Control for ON/OFF Keying and for Low Standby Power ConsumptionMinimal Frequency DriftZero Voltage Offset Due to Op-Amp BufferOperating Power-Supply Voltage RangeVCO Section...3V to 6VDigital Section...2V to 6VFanout (Over Temperature Range)Standard Outputs...10 LSTTL LoadsBus Driver Outputs...15 LSTTL LoadsWide Operating Temperature Range... –55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il≤ 1µA at VOL, VOHApplicationsFM Modulation and DemodulationFrequency Synthesis and MultiplicationFrequency DiscriminationTone DecodingData Synchronization and ConditioningVoltage-to-Frequency ConversionMotor-Speed ControlRelated LiteratureAN8823, CMOS Phase-Locked-Loop Application Using the CD74HC/HCT7046A and CD74HC/HCT7046A

Description

The CD74HC7046A and CD74HCT7046A high-speed silicon-gate CMOS devices, specified in compliance with JEDEC Standard No. 7A, are phase-locked-loop (PLL) circuits that contain a linear voltage-controlled oscillator (VCO), two-phase comparators (PC1, PC2), and a lock detector. A signal input and a comparator input are common to each comparator. The lock detector gives a HIGH level at pin 1 (LD) when the PLL is locked. The lock detector capacitor must be connected between pin 15 (CLD) and pin 8 (Gnd). For a frequency range of 100kHz to 10MHz, the lock detector capacitor should be 1000pF to 10pF, respectively. The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 7046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques. The CD74HC7046A and CD74HCT7046A high-speed silicon-gate CMOS devices, specified in compliance with JEDEC Standard No. 7A, are phase-locked-loop (PLL) circuits that contain a linear voltage-controlled oscillator (VCO), two-phase comparators (PC1, PC2), and a lock detector. A signal input and a comparator input are common to each comparator. The lock detector gives a HIGH level at pin 1 (LD) when the PLL is locked. The lock detector capacitor must be connected between pin 15 (CLD) and pin 8 (Gnd). For a frequency range of 100kHz to 10MHz, the lock detector capacitor should be 1000pF to 10pF, respectively. The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 7046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.