Catalog
PCIe3.0 12-Port/24-Lane Packet Switch
Key Features
• Port and Lane Configurations for 12-port/24-Lane PCI Express GEN3 packet switchConfigurable Upstream port number up to 2Configurable Upstream lane widths of x1, x2, x4 or x8Configurable Downstream port number up to 11Configurable Downstream lane widths of x1, x2, x4 or x8
• Configurable Upstream port number up to 2
• Configurable Upstream lane widths of x1, x2, x4 or x8
• Configurable Downstream port number up to 11
• Configurable Downstream lane widths of x1, x2, x4 or x8
• Reference Clock ManagementIntegrated PCIe Gen3 clock buffer for all downstream portsSupport three reference clock structures (Common, SRNS and SRIS)Handle SSC Isolation up to three portsProvide two clock application modes (Base and CDSR)
• Integrated PCIe Gen3 clock buffer for all downstream ports
• Support three reference clock structures (Common, SRNS and SRIS)
• Handle SSC Isolation up to three ports
• Provide two clock application modes (Base and CDSR)
• Power ManagementSupport 7 power states (P0/P0s/P1/P1.1/P1.2/P2/P1.2PG)Start-up power management scheme"Empty" Hot-Plug ports put in P2 state
• Support 7 power states (P0/P0s/P1/P1.1/P1.2/P2/P1.2PG)
• Start-up power management scheme"Empty" Hot-Plug ports put in P2 state
• "Empty" Hot-Plug ports put in P2 state
Description
AI
The PI7C9X3G1224GP is a PCIe®GEN3 packet switch that supports 24 lanes of GEN3 SERDES in flexible 3-port to 12-port configurations. The architecture of the PCIe packet switch allows the flexible port configuration by allocating variable lane width for each port. A basic cell of the switch architecture is called a tile, which consists of 8 ports and 16 lanes for Tile 0, 4 ports and 8 lanes for Tile 1. The PI7C9X3G1224GP is built with 2 tiles connected by internal signal paths. Each tile can be configured to have different port types such as upstream port and downstream ports to support various port configurations for fan-out application in single switch or dual-switch partition modes. Besides fan-out, there are some designated ports can be programmed as Cross-Domain End-Point (CDEP) ports to allow multiple hosts connected to the switch for fail-over or multiple-host computation and communication applications. Inside the packet switch, multiple DMA channels are embedded to facilitate data communication more efficiently among hosts.