CD54AC109 Series

Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset

Catalog

Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset

Part	Current - Quiescent (Iq)	Type	Trigger Type	Max CL	Max Propagation Delay	Clock Frequency	Input Capacitance	Mounting Type	Number of Bits per Element	Voltage - Supply (Maximum)	Voltage - Supply (Minimum)	Package Width	Package Name	Package Length	Function	Operating Temperature (Max)	Operating Temperature (Min)	Number of Elements	Output Type	Current - Output Low	Current - Output High
Texas Instruments CD54AC109F3A	4 µA	JK Type	Positive Edge	50 pF	10.3 ns	100 MHz	10 pF	Through Hole	1 bits	5.5 V	1.5 V	7.62 mm	16-CDIP	0.3 in	Set(Preset) and Reset	125 °C	-55 °C	2	Complementary	24 mA	24 mA

Catalog

Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset

Description

The CD74AC109-Q1 device contains two independent J-K positive edge triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs that meets the setup-time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. The device is qualified for automotive applications. The CD74AC109-Q1 device contains two independent J-K positive edge triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs that meets the setup-time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. The device is qualified for automotive applications.