CDCLVP1212 Series

Low jitter, 2-input selectable 1:12 universal-to-LVPECL buffer

Link to Manufacturer Page: https://www.ti.com/

Catalog

Low jitter, 2-input selectable 1:12 universal-to-LVPECL buffer

Part	Frequency - Max [Max]	Type	Output	Package / Case	Operating Temperature [Min]	Operating Temperature [Max]	Mounting Type	Input	Number of Circuits	Supplier Device Package	Voltage - Supply [Min]	Voltage - Supply [Max]	Ratio - Input:Output [custom]	Ratio - Input:Output [custom]	Supplied Contents	Function	Utilized IC / Part
Texas Instruments CDCLVP1212RHAT	2 GHz	Fanout Buffer (Distribution), Multiplexer	LVPECL	40-VFQFN Exposed Pad	-40 °C	85 °C	Surface Mount	LVCMOS, LVDS, LVPECL, LVTTL	1	40-VQFN (6x6)	2.375 V	3.6 V	2	12
Texas Instruments CDCLVP1212RHAR	2 GHz	Fanout Buffer (Distribution), Multiplexer	LVPECL	40-VFQFN Exposed Pad	-40 °C	85 °C	Surface Mount	LVCMOS, LVDS, LVPECL, LVTTL	1	40-VQFN (6x6)	2.375 V	3.6 V	2	12
Texas Instruments CDCLVP1212EVM		Timing													Board(s)	Clock Buffer	CDCLVP1212

Key Features

• 2:12 Differential BufferSelectable Clock Inputs Through Control TerminalUniversal Inputs Accept LVPECL, LVDS, andLVCMOS/LVTTL12 LVPECL OutputsMaximum Clock Frequency: 2 GHzMaximum Core Current Consumption: 88 mAVery Low Additive Jitter: <100 fs, rms in 10-kHz to20-MHz Offset Range:57 fs, rms (typ) @ 122.88 MHz48 fs, rms (typ) @ 156.25 MHz30 fs, rms (typ) @ 312.5 MHz2.375-V to 3.6-V Device Power SupplyMaximum Propagation Delay: 550 psMaximum Output Skew: 25 psLVPECL Reference Voltage, VAC_REF, Availablefor Capacitive-Coupled InputsIndustrial Temperature Range: –40°C to 85°CESD Protection Exceeds 2 kV (HBM)Supports 105°C PCB Temperature (Measuredwith a Thermal Pad)Available in 6-mm × 6-mm QFN-40 (RHA) Package2:12 Differential BufferSelectable Clock Inputs Through Control TerminalUniversal Inputs Accept LVPECL, LVDS, andLVCMOS/LVTTL12 LVPECL OutputsMaximum Clock Frequency: 2 GHzMaximum Core Current Consumption: 88 mAVery Low Additive Jitter: <100 fs, rms in 10-kHz to20-MHz Offset Range:57 fs, rms (typ) @ 122.88 MHz48 fs, rms (typ) @ 156.25 MHz30 fs, rms (typ) @ 312.5 MHz2.375-V to 3.6-V Device Power SupplyMaximum Propagation Delay: 550 psMaximum Output Skew: 25 psLVPECL Reference Voltage, VAC_REF, Availablefor Capacitive-Coupled InputsIndustrial Temperature Range: –40°C to 85°CESD Protection Exceeds 2 kV (HBM)Supports 105°C PCB Temperature (Measuredwith a Thermal Pad)Available in 6-mm × 6-mm QFN-40 (RHA) Package

Description

The CDCLVP1212 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1212 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 25 ps, making the device a perfect choice for use in demanding applications. The CDCLVP1212 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 12 pairs of differential LVPECL clock outputs (OUT0, OUT11) with minimum skew for clock distribution. The CDCLVP1212 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL. The CDCLVP1212 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended. The CDCLVP1212 is packaged in a small 40-terminal, 6-mm × 6-mm QFN package and is characterized for operation from –40°C to 85°C. The CDCLVP1212 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1212 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 25 ps, making the device a perfect choice for use in demanding applications. The CDCLVP1212 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 12 pairs of differential LVPECL clock outputs (OUT0, OUT11) with minimum skew for clock distribution. The CDCLVP1212 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL. The CDCLVP1212 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended. The CDCLVP1212 is packaged in a small 40-terminal, 6-mm × 6-mm QFN package and is characterized for operation from –40°C to 85°C.