74ABTH16260 Series
12-Bit To 24-Bit Multiplexed D-Type Latches With 3-State Outputs
Manufacturer: Texas Instruments
Catalog(1 parts)
| Part | Mounting Type | Independent Circuits▲▼ | Operating Temperature▲▼ | Operating Temperature▲▼ | Supplier Device Package | Output Type | Delay Time - Propagation▲▼ | Logic Type | Current - Output High, Low▲▼ | Package / Case▲▼ | Package / Case▲▼ | Package / Case | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Circuit |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Surface Mount | 1 ul | -40 °C | 85 °C | 56-SSOP | Tri-State | 3.2000000427245823e-9 s | D-Type Transparent Latch | 0.03200000151991844 A, 0.06400000303983688 A | 0.007493000011891127 m | 0.007499999832361937 m | 56-BSSOP | 5.5 V | 4.5 V | 12:24 |
Key Features
• Members of the Texas InstrumentsWidebusTMFamilyState-of-the-ArtEPIC-IIBTMBiCMOS Design Significantly Reduces Power DissipationESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17Typical VOLP(Output Ground Bounce) < 1 V at VCC= 5 V, TA= 25°CHigh-Impedance State During Power Up and Power DownDistributed VCCand GND Pin Configuration Minimizes High-Speed Switching NoiseFlow-Through Architecture Optimizes PCB LayoutHigh-Drive Outputs (-32-mA IOH, 64-mA IOL)Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsPackage Options Include Plastic 300-mil Shrink Small-Outline (DL) Package and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center SpacingsWidebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.Members of the Texas InstrumentsWidebusTMFamilyState-of-the-ArtEPIC-IIBTMBiCMOS Design Significantly Reduces Power DissipationESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17Typical VOLP(Output Ground Bounce) < 1 V at VCC= 5 V, TA= 25°CHigh-Impedance State During Power Up and Power DownDistributed VCCand GND Pin Configuration Minimizes High-Speed Switching NoiseFlow-Through Architecture Optimizes PCB LayoutHigh-Drive Outputs (-32-mA IOH, 64-mA IOL)Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsPackage Options Include Plastic 300-mil Shrink Small-Outline (DL) Package and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center SpacingsWidebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.
Description
AI
The SN54ABT16260 and SN74ABTH16260 are 12-bit to 24-bit multiplexed D-type latches used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing of address and data information in microprocessor or bus-interface applications. This device is also useful in memory-interleaving applications.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The output-enable (OE1B\, OE2B\, and OEA\) inputs control the bus-transceiver functions. The OE1B\ and OE2B\ control signals also allow bank control in the A-to-B direction.
Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains latched until the latch-enable input is returned high.
When VCCis between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ABT16260 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABTH16260 is characterized for operation from -40°C to 85°C.
The SN54ABT16260 and SN74ABTH16260 are 12-bit to 24-bit multiplexed D-type latches used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing of address and data information in microprocessor or bus-interface applications. This device is also useful in memory-interleaving applications.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The output-enable (OE1B\, OE2B\, and OEA\) inputs control the bus-transceiver functions. The OE1B\ and OE2B\ control signals also allow bank control in the A-to-B direction.
Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains latched until the latch-enable input is returned high.
When VCCis between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ABT16260 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABTH16260 is characterized for operation from -40°C to 85°C.