CDCVF2310-EP Series
Enhanced Product 2.5-V to 3.3-V high performance clock buffer
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
Enhanced Product 2.5-V to 3.3-V high performance clock buffer
| Part | Ratio - Input:Output [custom] | Ratio - Input:Output [custom] | Output | Operating Temperature [Max] | Operating Temperature [Min] | Voltage - Supply [Max] | Voltage - Supply [Min] | Type | Mounting Type | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Supplier Device Package | Package / Case [y] | Package / Case [y] | Package / Case | Frequency - Max [Max] | Number of Circuits |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments V62/13603-01XE | 1 | 10 | LVTTL | 125 ¯C | -55 °C | 3.6 V | 2.3 V | Clock Buffer | Surface Mount | 24-TSSOP | 4.4 mm | 0.173 " | 24-TSSOP | 200 MHz | 1 | ||
Texas Instruments CDCVF2310MPWEP | 1 | 10 | LVTTL | 125 ¯C | -55 °C | 3.6 V | 2.3 V | Fanout Buffer (Distribution) | Surface Mount | 24-TSSOP | 4.4 mm | 0.173 " | 24-TSSOP | 200 MHz | 1 | ||
Texas Instruments CDCVF2310MPWREP | 1 | 10 | LVTTL | 125 °C | -55 °C | 3.6 V | 2.3 V | Fanout Buffer (Distribution) | Surface Mount | 24-TSSOP | 4.4 mm | 0.173 " | 24-TSSOP | 200 MHz | 1 |
Key Features
• High-Performance 1:10 Clock DriverOperates up to 200 MHz at VDD3.3 VPin-to-Pin Skew < 100 ps at VDD3.3 VVDDRange: 2.3 V to 3.6 VOutput Enable Glitch SuppressionDistributes One Clock Input to Two Banks of Five Outputs25-Ω On-Chip Series Damping ResistorsPackaged in 24-Pin TSSOPHigh-Performance 1:10 Clock DriverOperates up to 200 MHz at VDD3.3 VPin-to-Pin Skew < 100 ps at VDD3.3 VVDDRange: 2.3 V to 3.6 VOutput Enable Glitch SuppressionDistributes One Clock Input to Two Banks of Five Outputs25-Ω On-Chip Series Damping ResistorsPackaged in 24-Pin TSSOP
Description
AI
The CDCVF2310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals.
The CDCVF2310 is characterized for operation from –55°C to 125°C.
The CDCVF2310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals.
The CDCVF2310 is characterized for operation from –55°C to 125°C.