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54HCT240 Series

Military 8-ch, 4.5-V to 5.5-V inverters with TTL-compatible CMOS inputs and 3-state outputs

Manufacturer: Texas Instruments

Catalog(1 parts)

PartNumber of Bits per ElementSupplier Device PackageNumber of ElementsMounting TypeCurrent - Output High, LowCurrent - Output High, LowPackage / CasePackage / CasePackage / CaseVoltage - SupplyVoltage - SupplyLogic TypeOutput TypeOperating TemperatureOperating Temperature
Texas Instruments
SNJ54HCT240J
Buffer, Inverting 2 Element 4 Bit per Element 3-State Output 20-CDIP
4 ul
20-CDIP
2 ul
Through Hole
0.006000000052154064 A
0.006000000052154064 A
0.007619999814778566 m
0.007619999814778566 m
20-CDIP
5.5 V
4.5 V
Buffer, Inverting
3-State
-55 °C
125 °C

Key Features

Operating voltage range of 4.5V to 5.5VHigh-current outputs drive up to 15 LSTTL loadsLow power consumption, 80µA max ICCTypical tpd = 12 ns±6mA output drive at 5VLow input current of 1µA maxInputs are TTL-voltage compatible3-state outputs drive bus lines or buffer memory address registersOperating voltage range of 4.5V to 5.5VHigh-current outputs drive up to 15 LSTTL loadsLow power consumption, 80µA max ICCTypical tpd = 12 ns±6mA output drive at 5VLow input current of 1µA maxInputs are TTL-voltage compatible3-state outputs drive bus lines or buffer memory address registers

Description

AI
These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HCT240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HCT240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.