ADC32J44 Series
Dual-Channel, 14-Bit, 125-MSPS Analog-to-Digital Converter (ADC)
Manufacturer: Texas Instruments
Catalog(2 parts)
| Part | Package / Case | Number of Inputs▲▼ | Features | Voltage - Supply, Digital▲▼ | Voltage - Supply, Digital▲▼ | Mounting Type | Input Type | Reference Type | Number of Bits▲▼ | Configuration | Sampling Rate (Per Second)▲▼ | Number of A/D Converters▲▼ | Architecture | Data Interface | Operating Temperature▲▼ | Operating Temperature▲▼ | Supplier Device Package | Voltage - Supply, Analog▲▼ | Voltage - Supply, Analog▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
48-VFQFN Exposed Pad | 2 ul | Simultaneous Sampling | 1.7000000476837158 V | 1.899999976158142 V | Surface Mount | Differential | External, Internal | 14 ul | ADC | 125 m | 2 ul | Pipelined | JESD204B | -40 °C | 85 °C | 48-VQFN (7x7) | 1.7000000476837158 V | 1.899999976158142 V | |
48-VFQFN Exposed Pad | Surface Mount | 48-VQFN (7x7) |
Key Features
• Dual Channel14-Bit ResolutionSingle Supply: 1.8 VFlexible Input Clock Buffer with Divide-by-1, -2, -4SNR = 72.2 dBFS, SFDR = 87 dBc atfIN= 70 MHzUltralow Power Consumption:227 mW/Ch at 160 MSPSChannel Isolation: 105 dBInternal DitherJESD204B Serial Interface:Subclass 0, 1, 2 Compliant up to 3.2 GbpsSupports One Lane per ADC up to 160 MSPSSupport for Multichip SynchronizationPin-to-Pin Compatible with 12-Bit Version(ADC32J2X)Package: VQFN-48 (7 mm × 7 mm)Dual Channel14-Bit ResolutionSingle Supply: 1.8 VFlexible Input Clock Buffer with Divide-by-1, -2, -4SNR = 72.2 dBFS, SFDR = 87 dBc atfIN= 70 MHzUltralow Power Consumption:227 mW/Ch at 160 MSPSChannel Isolation: 105 dBInternal DitherJESD204B Serial Interface:Subclass 0, 1, 2 Compliant up to 3.2 GbpsSupports One Lane per ADC up to 160 MSPSSupport for Multichip SynchronizationPin-to-Pin Compatible with 12-Bit Version(ADC32J2X)Package: VQFN-48 (7 mm × 7 mm)
Description
AI
The ADC32J4x are a high-linearity, ultra-low power, dual-channel, 14-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC32J4x family supports JESD204B interface in order to reduce the number of interface lines, thus allowing high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock, which is used to serialize the 14-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps.
The ADC32J4x are a high-linearity, ultra-low power, dual-channel, 14-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC32J4x family supports JESD204B interface in order to reduce the number of interface lines, thus allowing high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock, which is used to serialize the 14-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps.