Catalog(2 parts)
| Part | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Number of Bits per Element▲▼ | Logic Type | Package / Case▲▼ | Package / Case▲▼ | Package / Case | Trigger Type | Count Rate▲▼ | Reset | Mounting Type | Number of Elements▲▼ | Supplier Device Package | Operating Temperature▲▼ | Operating Temperature▲▼ | Direction |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
4.75 V | 5.25 V | 4 ul | Divide-by-12 | 0.0052999998442828655 m | 0.005308600142598152 m | 14-SOIC | Positive Edge | 42000000 Hz | Synchronous | Surface Mount | 1 ul | 14-SO | 70 °C | 0 °C | Up | |
Key Features
• '90A, 'LS90 . . . Decade Counters'92A, 'LS92 . . . Divide By-Twelve Counters'93A, 'LS93 . . . 4-Bit Binary CountersTYPESTYPICALPOWER DISSIPATION'90A145 mW'92A, '93A130 mW'LS90, 'LS92, 'LS9345 mW'90A, 'LS90 . . . Decade Counters'92A, 'LS92 . . . Divide By-Twelve Counters'93A, 'LS93 . . . 4-Bit Binary CountersTYPESTYPICALPOWER DISSIPATION'90A145 mW'92A, '93A130 mW'LS90, 'LS92, 'LS9345 mW
Description
AI
Each of these monolithic counters contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-five for the '90A and 'LS90, divide-by-six for the '92A and 'LS92, and the divide-by eight for the '93A and 'LS93.
All of these counters have a gated zero reset and the '90A and 'LS90 also have gated set-to-nine inputs for use in BCD nine's complement applications.
To use their maximum count length (decade, divide-by-twelve, or four-bit binary) of these counters, the CKB input is connected to the QAoutput. The input count pulses are applied to CKA input and the outputs are as described in the appropriate function table. A symmetrical divide-by-ten count can be obtained from the '90A or 'LS90 counters by connecting the QDoutput to the CKA input and applying the input count to the CKB input which gives a divide-by-ten square wave at output QA.
Each of these monolithic counters contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-five for the '90A and 'LS90, divide-by-six for the '92A and 'LS92, and the divide-by eight for the '93A and 'LS93.
All of these counters have a gated zero reset and the '90A and 'LS90 also have gated set-to-nine inputs for use in BCD nine's complement applications.
To use their maximum count length (decade, divide-by-twelve, or four-bit binary) of these counters, the CKB input is connected to the QAoutput. The input count pulses are applied to CKA input and the outputs are as described in the appropriate function table. A symmetrical divide-by-ten count can be obtained from the '90A or 'LS90 counters by connecting the QDoutput to the CKA input and applying the input count to the CKB input which gives a divide-by-ten square wave at output QA.