74ALVTH16374 Series
2.5-V/3.3-V 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs
Manufacturer: Texas Instruments
Catalog(2 parts)
| Part | Max Propagation Delay @ V, Max CL▲▼ | Number of Elements▲▼ | Input Capacitance▲▼ | Trigger Type | Type | Mounting Type | Clock Frequency▲▼ | Current - Output High, Low▲▼ | Current - Output High, Low▲▼ | Output Type | Supplier Device Package | Operating Temperature▲▼ | Operating Temperature▲▼ | Function | Current - Quiescent (Iq)▲▼ | Package / Case▲▼ | Package / Case | Package / Case▲▼ | Number of Bits per Element▲▼ | Voltage - Supply▲▼ | Voltage - Supply▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments SN74ALVTH16374GRFlip Flop 2 Element D-Type 8 Bit Positive Edge 48-TFSOP (0.240", 6.10mm Width) | 3.2000000427245823e-9 s | 2 ul | 3.4999999860146898e-12 F | Positive Edge | D-Type | Surface Mount | 250000000 Hz | 0.00800000037997961 A, 0.03200000151991844 A | 0.024000000208616257 A, 0.06400000303983688 A | Tri-State, Non-Inverted | 48-TSSOP | 85 °C | -40 °C | Standard | 0.00009999999747378752 A | 0.006099999882280827 m | 48-TFSOP | 0.006095999851822853 m | 8 ul | 2.700000047683716 V, 3.5999999046325684 V | 2.299999952316284 V, 3 V |
3.2000000427245823e-9 s | 2 ul | 3.4999999860146898e-12 F | Positive Edge | D-Type | Surface Mount | 250000000 Hz | 0.00800000037997961 A, 0.03200000151991844 A | 0.024000000208616257 A, 0.06400000303983688 A | Tri-State, Non-Inverted | 56-BGA Microstar Junior (7x4.5) | 85 °C | -40 °C | Standard | 0.00009999999747378752 A | 56-VFBGA | 8 ul | 2.700000047683716 V, 3.5999999046325684 V | 2.299999952316284 V, 3 V |
Key Features
• State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus™ Design for 2.5-V and 3.3-V Operation and Low Static Power DissipationSupport Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC)Typical VOLP(Output Ground Bounce) <0.8 V at VCC= 3.3 V, TA= 25°CHigh Drive (-24/24 mA at 2.5-V VCCand -32/64 mA at 3.3-V )Power Off Disables Outputs, Permitting Live InsertionHigh-Impedance State During Power Up and Power Down Prevents Driver ConflictUses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From FloatingAuto3-State Eliminates Bus Current Loading When Output Exceeds VCC+ 0.5 VLatch-Up Performance Exceeds 250 mA Per JESD 17ESD ProtectionExceeds 2000 V Per MIL-STD-883, Method 3015Exceeds 200 V Using Machine ModelExceeds 1000 V Using Charged-Device Model, Robotic MethodFlow-Through Architecture Facilitates Printed Circuit Board LayoutDistributed VCCand GND Pin Configuration Minimizes High-Speed Switching NoisePackage Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) PackageWidebus is a trademark of Texas Instruments.State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus™ Design for 2.5-V and 3.3-V Operation and Low Static Power DissipationSupport Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC)Typical VOLP(Output Ground Bounce) <0.8 V at VCC= 3.3 V, TA= 25°CHigh Drive (-24/24 mA at 2.5-V VCCand -32/64 mA at 3.3-V )Power Off Disables Outputs, Permitting Live InsertionHigh-Impedance State During Power Up and Power Down Prevents Driver ConflictUses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From FloatingAuto3-State Eliminates Bus Current Loading When Output Exceeds VCC+ 0.5 VLatch-Up Performance Exceeds 250 mA Per JESD 17ESD ProtectionExceeds 2000 V Per MIL-STD-883, Method 3015Exceeds 200 V Using Machine ModelExceeds 1000 V Using Charged-Device Model, Robotic MethodFlow-Through Architecture Facilitates Printed Circuit Board LayoutDistributed VCCand GND Pin Configuration Minimizes High-Speed Switching NoisePackage Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) PackageWidebus is a trademark of Texas Instruments.
Description
AI
The 'ALVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.
OEdoes not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When VCCis between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ALVTH16374 is characterized for operation over the full military temperature range of -55°C to 125°C.
The SN74ALVTH16374 is characterized for operation from -40°C to 85°C.
The 'ALVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.
OEdoes not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When VCCis between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ALVTH16374 is characterized for operation over the full military temperature range of -55°C to 125°C.
The SN74ALVTH16374 is characterized for operation from -40°C to 85°C.