74ABT16843 Series
18-Bit Bus-Interface D-Type Latches With 3-State Outputs
Manufacturer: Texas Instruments
Catalog(2 parts)
| Part | Delay Time - Propagation▲▼ | Operating Temperature▲▼ | Operating Temperature▲▼ | Package / Case | Package / Case▲▼ | Package / Case▲▼ | Logic Type | Supplier Device Package | Current - Output High, Low▲▼ | Independent Circuits▲▼ | Mounting Type | Circuit▲▼ | Circuit▲▼ | Output Type | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Package / Case▲▼ | Package / Case▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
3.999999886872274e-9 s | -40 °C | 85 °C | 56-TFSOP | 0.006099999882280827 m | 0.006095999851822853 m | D-Type Transparent Latch | 56-TSSOP | 0.03200000151991844 A, 0.06400000303983688 A | 2 ul | Surface Mount | 9 ul | 9 ul | Tri-State | 5.5 V | 4.5 V | |||
3.999999886872274e-9 s | -40 °C | 85 °C | 56-BSSOP | D-Type Transparent Latch | 56-SSOP | 0.03200000151991844 A, 0.06400000303983688 A | 2 ul | Surface Mount | 9 ul | 9 ul | Tri-State | 5.5 V | 4.5 V | 0.007493000011891127 m | 0.007499999832361937 m |
Key Features
• Members of the Texas InstrumentsWidebusTMFamilyState-of-the-ArtEPIC-IIBTMBiCMOS Design Significantly Reduces Power DissipationDistributed VCCand GND Pin Configuration Minimizes High-Speed Switching NoiseFlow-Through Architecture Optimizes PCB LayoutHigh-Impedance State During Power Up and Power DownHigh-Drive Outputs (-32-mA IOH, 64-mA IOL)Package Options Include Plastic Thin Shrink Small-Outline (DGG), 300-mil Shrink Small-Outline (DL) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center SpacingsWidebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.Members of the Texas InstrumentsWidebusTMFamilyState-of-the-ArtEPIC-IIBTMBiCMOS Design Significantly Reduces Power DissipationDistributed VCCand GND Pin Configuration Minimizes High-Speed Switching NoiseFlow-Through Architecture Optimizes PCB LayoutHigh-Impedance State During Power Up and Power DownHigh-Drive Outputs (-32-mA IOH, 64-mA IOL)Package Options Include Plastic Thin Shrink Small-Outline (DGG), 300-mil Shrink Small-Outline (DL) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center SpacingsWidebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.
Description
AI
The 'ABT16843 18-bit bus-interface D-type latches are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The 'ABT16843 can be used as two 9-bit latches or one 18-bit latch. The 18 latches are transparent D-type latches. The device provides true data at its outputs.
A buffered output-enable (OE\) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The outputs are in the high-impedance state during power up and power down. The outputs remain in the high-impedance state while the device is powered down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.
When VCCis between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16843 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16843 is characterized for operation from -40°C to 85°C.
The 'ABT16843 18-bit bus-interface D-type latches are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The 'ABT16843 can be used as two 9-bit latches or one 18-bit latch. The 18 latches are transparent D-type latches. The device provides true data at its outputs.
A buffered output-enable (OE\) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The outputs are in the high-impedance state during power up and power down. The outputs remain in the high-impedance state while the device is powered down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.
When VCCis between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16843 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16843 is characterized for operation from -40°C to 85°C.