74ALVTH16821 Series
2.5-V/3.3-V 20-Bit Bus-Interface Flip-Flops With 3-State Outputs
Manufacturer: Texas Instruments
Catalog(2 parts)
| Part | Function | Clock Frequency▲▼ | Number of Elements▲▼ | Supplier Device Package | Mounting Type | Max Propagation Delay @ V, Max CL▲▼ | Operating Temperature▲▼ | Operating Temperature▲▼ | Trigger Type | Input Capacitance▲▼ | Output Type | Number of Bits per Element▲▼ | Current - Quiescent (Iq)▲▼ | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Current - Output High, Low▲▼ | Current - Output High, Low▲▼ | Package / Case▲▼ | Package / Case | Package / Case▲▼ | Type | Package / Case▲▼ | Package / Case▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments SN74ALVTH16821VRFlip Flop 2 Element D-Type 10 Bit Positive Edge 56-TFSOP (0.173", 4.40mm Width) | Standard | 150000000 Hz | 2 ul | 56-TVSOP | Surface Mount | 3.500000067546693e-9 s | 85 °C | -40 °C | Positive Edge | 3.4999999860146898e-12 F | Tri-State, Non-Inverted | 10 ul | 0.00009999999747378752 A | 2.700000047683716 V, 3.5999999046325684 V | 2.299999952316284 V, 3 V | 0.00800000037997961 A, 0.03200000151991844 A | 0.024000000208616257 A, 0.06400000303983688 A | 0.004399999976158142 m | 56-TFSOP | 0.004394200164824724 m | D-Type | ||
Texas Instruments SN74ALVTH16821DLRFlip Flop 2 Element D-Type 10 Bit Positive Edge 56-BSSOP (0.295", 7.50mm Width) | Standard | 150000000 Hz | 2 ul | 56-SSOP | Surface Mount | 3.500000067546693e-9 s | 85 °C | -40 °C | Positive Edge | 3.4999999860146898e-12 F | Tri-State, Non-Inverted | 10 ul | 0.00009999999747378752 A | 2.700000047683716 V, 3.5999999046325684 V | 2.299999952316284 V, 3 V | 0.00800000037997961 A, 0.03200000151991844 A | 0.024000000208616257 A, 0.06400000303983688 A | 56-BSSOP | D-Type | 0.007493000011891127 m | 0.007499999832361937 m |
Key Features
• State-of-the-Art Advanced BiCMOS Technology (ABT)WidebusTMDesign for 2.5-V and 3.3-V Operation and Low Static Power DissipationSupport Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC)Typical VOLP(Output Ground Bounce) < 0.8 V at VCC= 3.3 V, TA= 25°CHigh-Drive (-24/24 mA at 2.5-V and-32/64 mA at 3.3-V VCC)Power Off Disables Outputs, Permitting Live InsertionHigh-Impedance State During Power Up and Power Down Prevents Driver ConflictUses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From FloatingAuto3-State Eliminates Bus Current Loading When Output Exceeds VCC+ 0.5 VLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model; and Exceeds 1000 V Using Charged-Device Model, Robotic MethodFlow-Through Architecture Facilitates Printed Circuit Board LayoutDistributed VCCand GND Pin Configuration Minimizes High-Speed Switching NoisePackage Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) PackageWidebus is a trademark of Texas Instruments Incorporated.State-of-the-Art Advanced BiCMOS Technology (ABT)WidebusTMDesign for 2.5-V and 3.3-V Operation and Low Static Power DissipationSupport Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC)Typical VOLP(Output Ground Bounce) < 0.8 V at VCC= 3.3 V, TA= 25°CHigh-Drive (-24/24 mA at 2.5-V and-32/64 mA at 3.3-V VCC)Power Off Disables Outputs, Permitting Live InsertionHigh-Impedance State During Power Up and Power Down Prevents Driver ConflictUses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From FloatingAuto3-State Eliminates Bus Current Loading When Output Exceeds VCC+ 0.5 VLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model; and Exceeds 1000 V Using Charged-Device Model, Robotic MethodFlow-Through Architecture Facilitates Printed Circuit Board LayoutDistributed VCCand GND Pin Configuration Minimizes High-Speed Switching NoisePackage Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) PackageWidebus is a trademark of Texas Instruments Incorporated.
Description
AI
The 'ALVTH16821 devices are 20-bit bus-interface flip-flops with 3-state outputs designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.
The devices can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20-bit flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the D inputs.
A buffered output-enable (OE\) input can be used to place the ten outputs in either a normal logic state (high or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
When VCCis between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ALVTH16821 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16821 is characterized for operation from -40°C to 85°C.
The 'ALVTH16821 devices are 20-bit bus-interface flip-flops with 3-state outputs designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.
The devices can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20-bit flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the D inputs.
A buffered output-enable (OE\) input can be used to place the ten outputs in either a normal logic state (high or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
When VCCis between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ALVTH16821 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16821 is characterized for operation from -40°C to 85°C.