CD74HC138-Q1 Series
Automotive Catalog High Speed CMOS Logic 3-to-8 Line Decoder Demultiplexer Inverting and Non-Invert
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
Automotive Catalog High Speed CMOS Logic 3-to-8 Line Decoder Demultiplexer Inverting and Non-Invert
| Part | Mounting Type | Independent Circuits | Current - Output High, Low | Grade | Type | Voltage Supply Source | Circuit | Package / Case | Package / Case | Voltage - Supply [Min] | Voltage - Supply [Max] | Supplier Device Package | Qualification | Operating Temperature [Max] | Operating Temperature [Min] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD74HC138QM96Q1 | Surface Mount | 1 | 5.2 mA, 5.2 mA | Automotive | Decoder/Demultiplexer | Single Supply | 1 x 3:8 | 16-SOIC | 0.154 in, 3.9 mm Width | 2 V | 6 V | 16-SOIC | AEC-Q100 | 125 °C | -40 °C |
Key Features
• Qualified for Automotive ApplicationsSelect One of Eight Data Outputs Active LowI/O Port or Memory SelectorThree Enable Inputs to Simplify CascadingTypical Propagation Delay of 13 ns at VCC= 5 V, CL= 15 pF, TA= 25°CFanout (Over Temperature Range)Standard Outputs . . . 10 LSTTL LoadsBus Driver Outputs . . . 15 LSTTL LoadsBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICs2-V to 6-V VCCOperationHigh Noise Immunity; NILor NIH= 30% of VCC, VCC= 5 VQualified for Automotive ApplicationsSelect One of Eight Data Outputs Active LowI/O Port or Memory SelectorThree Enable Inputs to Simplify CascadingTypical Propagation Delay of 13 ns at VCC= 5 V, CL= 15 pF, TA= 25°CFanout (Over Temperature Range)Standard Outputs . . . 10 LSTTL LoadsBus Driver Outputs . . . 15 LSTTL LoadsBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICs2-V to 6-V VCCOperationHigh Noise Immunity; NILor NIH= 30% of VCC, VCC= 5 V
Description
AI
The CD74HC138 is a high-speed silicon-gate CMOS decoder well suited to memory address decoding or data routing applications. This circuit features low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low-power Schottky TTL logic. The circuit has three binary select inputs (A0, A1, and A2). If the device is enabled, these inputs determine which one of the eight normally high outputs of the HC138 will go low.
Two active-low and one active-high enables (E1,E2, and E3) are provided to ease the cascading of decoders. The decoder’s eight outputs can drive ten low-power Schottky TTL equivalent loads.
The CD74HC138 is a high-speed silicon-gate CMOS decoder well suited to memory address decoding or data routing applications. This circuit features low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low-power Schottky TTL logic. The circuit has three binary select inputs (A0, A1, and A2). If the device is enabled, these inputs determine which one of the eight normally high outputs of the HC138 will go low.
Two active-low and one active-high enables (E1,E2, and E3) are provided to ease the cascading of decoders. The decoder’s eight outputs can drive ten low-power Schottky TTL equivalent loads.