Catalog(4 parts)
| Part | Function | Operating Temperature▲▼ | Operating Temperature▲▼ | Supplier Device Package | Mounting Type | Output Type | Input Capacitance▲▼ | Number of Bits per Element▲▼ | Max Propagation Delay @ V, Max CL▲▼ | Current - Quiescent (Iq)▲▼ | Package / Case | Number of Elements▲▼ | Current - Output High, Low▲▼ | Current - Output High, Low▲▼ | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Type | Trigger Type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Standard | -40 °C | 125 °C | 6-DSBGA | Surface Mount | Tri-State | 2.9999999880125916e-12 F | 1 ul | 3.999999886872274e-9 s | 0.000009999999747378752 A | 6-XFBGA, DSBGA | 1 ul | 0.03200000151991844 A | 0.03200000151991844 A | 5.5 V | 1.649999976158142 V | D-Type | Positive Edge | |
Standard | -40 °C | 125 °C | SOT-23-6 | Surface Mount | Tri-State | 2.9999999880125916e-12 F | 1 ul | 3.999999886872274e-9 s | 0.000009999999747378752 A | SOT-23-6 | 1 ul | 0.03200000151991844 A | 0.03200000151991844 A | 5.5 V | 1.649999976158142 V | D-Type | Positive Edge | |
Texas Instruments 74LVC1G374DCKRG4Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-TSSOP, SC-88, SOT-363 | Standard | -40 °C | 125 °C | SC-70-6 | Surface Mount | Tri-State | 2.9999999880125916e-12 F | 1 ul | 3.999999886872274e-9 s | 0.000009999999747378752 A | 6-TSSOP, SC-88, SOT-363 | 1 ul | 0.03200000151991844 A | 0.03200000151991844 A | 5.5 V | 1.649999976158142 V | D-Type | Positive Edge |
Texas Instruments SN74LVC1G374DCKRFlip Flop 1 Element D-Type 1 Bit Positive Edge 6-TSSOP, SC-88, SOT-363 | Standard | -40 °C | 125 °C | SC-70-6 | Surface Mount | Tri-State | 2.9999999880125916e-12 F | 1 ul | 3.999999886872274e-9 s | 10 ul | 6-TSSOP, SC-88, SOT-363 | 1 ul | 0.03200000151991844 A | 0.03200000151991844 A | 5.5 V | 1.649999976158142 V | D-Type | Positive Edge |
Key Features
• Available in the Texas Instruments NanoStar and NanoFree PackagesSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VProvides Down Translation to VCCMax tpdof 4 ns at 3.3 VLow Power Consumption, 10-μA Max ICC±24-mA Output Drive at 3.3 VIoffSupports Live Insertion, Partial-Power-Down Mode, and Back Drive ProtectionLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Available in the Texas Instruments NanoStar and NanoFree PackagesSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VProvides Down Translation to VCCMax tpdof 4 ns at 3.3 VLow Power Consumption, 10-μA Max ICC±24-mA Output Drive at 3.3 VIoffSupports Live Insertion, Partial-Power-Down Mode, and Back Drive ProtectionLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)
Description
AI
This single D-type latch is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC1G374 features a 3-state output designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
On the positive transition of the clock (CLK) input, the Q output is set to the logic level set up at the data (D) input.
A buffered output-enable (OE) input can be used to place the output in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OEdoes not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This single D-type latch is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC1G374 features a 3-state output designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
On the positive transition of the clock (CLK) input, the Q output is set to the logic level set up at the data (D) input.
A buffered output-enable (OE) input can be used to place the output in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OEdoes not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.