TPS70751 Series

The TPS707xx family devices are designed to provide a complete power-management solution for TI DSP, processor power, ASIC, FPGA, and digital applications where dual-output voltage regulators are required. Easy programmability of the sequencing function makes this family ideal for any TI DSP applications with power-sequencing requirements. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power-on reset), manual reset inputs, and enable function, provide a complete system solution. The TPS707xx family of voltage regulators offer very low dropout (LDO) voltage and dual outputs with power-up sequence control, which is designed primarily for DSP applications. These devices have extremely low noise output performance without using any added filter bypass capacitors, and are designed to have a fast transient response and be stable with 10-µF low ESR capacitors. The TPS70751 has a fixed voltage of 3.3 V/1.8 V. Regulator 1 can support up to 250 mA and regulator 2 can support up to 125 mA. Separate voltage inputs allow the designer to configure the source power. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 83 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230 µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal toEN(enable) shuts down both regulators, reducing the input current to 1 µA at TJ= 25°C. The device is enabled when the enable (EN) pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1and VSENSE2pins, respectively. The input signal at the sequence (SEQ) pin controls the power-up sequence of the two regulators. When the device is enabled and SEQ is pulled high or left open, VOUT2turns on first and VOUT1remains off until VOUT2reaches approximately 83% of its regulated output voltage. At that time, VOUT1is turned on. If VOUT2is pulled below 83% (i.e., overload condition), VOUT1is turned off. Pulling SEQ low reverses the power-up order and VOUT1is turned on first. SEQ is connected to an internal pullup current source. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The power good (PG1) pin reports the voltage conditions at VOUT1. Power good can be used to implement a SVS for the circuitry supplied by regulator 1. The TPS70751 features aRESET(SVS, POR, or power-on reset). TheRESEToutput initiates a reset in DSP systems and related digital applications in the event of an undervoltage condition.RESETindicates the status of VOUT2and both manual reset (MR1andMR2) pins. When VOUT2reaches 95% of its regulated voltage andMR1andMR2are in the logic high state,RESETgoes to a high-impedance state after a 120-ms delay.RESETgoes to logic low state when VOUT2regulated output voltage is pulled below 95% (i.e., overload condition) of its regulated voltage. To monitor VOUT1, the PG1 output can be connected toMR1orMR2. The device has an undervoltage lockout (UVLO) circuit that prevents the internal regulators from turning on until VIN1reaches 2.5 V. The TPS707xx family devices are designed to provide a complete power-management solution for TI DSP, processor power, ASIC, FPGA, and digital applications where dual-output voltage regulators are required. Easy programmability of the sequencing function makes this family ideal for any TI DSP applications with power-sequencing requirements. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power-on reset), manual reset inputs, and enable function, provide a complete system solution. The TPS707xx family of voltage regulators offer very low dropout (LDO) voltage and dual outputs with power-up sequence control, which is designed primarily for DSP applications. These devices have extremely low noise output performance without using any added filter bypass capacitors, and are designed to have a fast transient response and be stable with 10-µF low ESR capacitors. The TPS70751 has a fixed voltage of 3.3 V/1.8 V. Regulator 1 can support up to 250 mA and regulator 2 can support up to 125 mA. Separate voltage inputs allow the designer to configure the source power. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 83 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230 µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal toEN(enable) shuts down both regulators, reducing the input current to 1 µA at TJ= 25°C. The device is enabled when the enable (EN) pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1and VSENSE2pins, respectively. The input signal at the sequence (SEQ) pin controls the power-up sequence of the two regulators. When the device is enabled and SEQ is pulled high or left open, VOUT2turns on first and VOUT1remains off until VOUT2reaches approximately 83% of its regulated output voltage. At that time, VOUT1is turned on. If VOUT2is pulled below 83% (i.e., overload condition), VOUT1is turned off. Pulling SEQ low reverses the power-up order and VOUT1is turned on first. SEQ is connected to an internal pullup current source. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The power good (PG1) pin reports the voltage conditions at VOUT1. Power good can be used to implement a SVS for the circuitry supplied by regulator 1. The TPS70751 features aRESET(SVS, POR, or power-on reset). TheRESEToutput initiates a reset in DSP systems and related digital applications in the event of an undervoltage condition.RESETindicates the status of VOUT2and both manual reset (MR1andMR2) pins. When VOUT2reaches 95% of its regulated voltage andMR1andMR2are in the logic high state,RESETgoes to a high-impedance state after a 120-ms delay.RESETgoes to logic low state when VOUT2regulated output voltage is pulled below 95% (i.e., overload condition) of its regulated voltage. To monitor VOUT1, the PG1 output can be connected toMR1orMR2. The device has an undervoltage lockout (UVLO) circuit that prevents the internal regulators from turning on until VIN1reaches 2.5 V.