ADC3242 Series
Dual-Channel, 14-Bit, 50-MSPS Analog-to-Digital Converter (ADC)
Manufacturer: Texas Instruments
Catalog(1 parts)
| Part | Architecture | Voltage - Supply, Analog▲▼ | Voltage - Supply, Analog▲▼ | Data Interface | Number of Bits▲▼ | Number of Inputs▲▼ | Mounting Type | Reference Type | Supplier Device Package | Package / Case | Input Type | Voltage - Supply, Digital▲▼ | Voltage - Supply, Digital▲▼ | Number of A/D Converters▲▼ | Sampling Rate (Per Second)▲▼ | Features | Configuration | Operating Temperature▲▼ | Operating Temperature▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Pipelined | 1.7000000476837158 V | 1.899999976158142 V | LVDS - Serial | 14 ul | 2 ul | Surface Mount | External, Internal | 48-VQFN (7x7) | 48-VFQFN Exposed Pad | Differential | 1.7000000476837158 V | 1.899999976158142 V | 2 ul | 50 m | Simultaneous Sampling | ADC | -40 °C | 85 °C |
Key Features
• Dual Channel14-Bit ResolutionSingle Supply: 1.8 VSerial LVDS Interface (SLVDS)Flexible Input Clock Buffer with Divide-by-1, -2, -4SNR = 72.4 dBFS, SFDR = 87 dBc atfIN= 70 MHzUltra-Low Power Consumption:116 mW/Ch at 125 MSPSChannel Isolation: 105 dBInternal Dither and ChopperSupport for Multi-Chip SynchronizationPin-to-Pin Compatible with 12-Bit VersionPackage: VQFN-48 (7 mm × 7 mm)Dual Channel14-Bit ResolutionSingle Supply: 1.8 VSerial LVDS Interface (SLVDS)Flexible Input Clock Buffer with Divide-by-1, -2, -4SNR = 72.4 dBFS, SFDR = 87 dBc atfIN= 70 MHzUltra-Low Power Consumption:116 mW/Ch at 125 MSPSChannel Isolation: 105 dBInternal Dither and ChopperSupport for Multi-Chip SynchronizationPin-to-Pin Compatible with 12-Bit VersionPackage: VQFN-48 (7 mm × 7 mm)
Description
AI
The ADC324x are a high-linearity, ultra-low power, dual-channel, 14-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC324x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.
The ADC324x are a high-linearity, ultra-low power, dual-channel, 14-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC324x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.