74HCS164 Series

8-bit serial-in/parallel-out shift register

Catalog(3 parts)

Part	Qualification	Function	Number of Bits per Element▲▼	Grade	Voltage - Supply▲▼	Voltage - Supply▲▼	Package / Case▲▼	Package / Case▲▼	Package / Case	Number of Elements▲▼	Output Type	Operating Temperature▲▼	Operating Temperature▲▼	Mounting Type	Logic Type	Supplier Device Package	Package / Case▲▼	Package / Case▲▼
Texas Instruments SN74HCS164QDRQ1 Shift Shift Register 1 Element 8 Bit 14-SOIC	AEC-Q100	Serial to Parallel	8 ul	Automotive	2 V	6 V	0.003899999894201755 m	0.003911599982529879 m	14-SOIC	1 ul	Push-Pull	-40 °C	125 °C	Surface Mount	Shift Register
Texas Instruments SN74HCS164QPWRQ1 Shift Shift Register 1 Element 8 Bit 14-TSSOP	AEC-Q100	Serial to Parallel	8 ul	Automotive	2 V	6 V			14-TSSOP	1 ul	Push-Pull	-40 °C	125 °C	Surface Mount	Shift Register	14-TSSOP	0.004394200164824724 m	0.004399999976158142 m
Texas Instruments SN74HCS164BQAR Shift Shift Register 1 Element 8 Bit 14-WQFN (3x2.5)		Serial to Parallel	8 ul		2 V	6 V			14-QFN Exposed Pad	1 ul	Push-Pull	-40 °C	125 °C	Surface Mount	Shift Register	14-WQFN (3x2.5)

Key Features

• Wide operating voltage range: 2 V to 6 VSchmitt-trigger inputs allow for slow or noisy input signalsLow power consumptionTypical ICCof 100 nATypical input leakage current of ±100 nA±7.8-mA output drive at 6 VExtended ambient temperature range: –40°C to +125°C, TAWide operating voltage range: 2 V to 6 VSchmitt-trigger inputs allow for slow or noisy input signalsLow power consumptionTypical ICCof 100 nATypical input leakage current of ±100 nA±7.8-mA output drive at 6 VExtended ambient temperature range: –40°C to +125°C, TA

Description

The SN74HCS164 device contains an 8-bit shift register with AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The SN74HCS164 device contains an 8-bit shift register with AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals.