SPC570S50E1 Series

32-bit Power Architecture MCU for Automotive Chassis and Safety Applications

Catalog

32-bit Power Architecture MCU for Automotive Chassis and Safety Applications

Part	Voltage - Supply (Vcc/Vdd) [Max]	Voltage - Supply (Vcc/Vdd) [Min]	Connectivity	EEPROM Size	Grade	Peripherals	Core Size	Oscillator Type	Core Processor	Data Converters	Data Converters	Data Converters [custom]	Program Memory Size	Speed	Package / Case	Supplier Device Package	Mounting Type	Qualification	Program Memory Type	Operating Temperature [Min]	Operating Temperature [Max]	Data Converters [custom]
STMicroelectronics SPC570S50E1DEFAY	5.5 V	3 V	CANbus LINbus SPI UART/USART	32 K	Automotive	DMA POR WDT	32-Bit Single-Core	External	e200z0h	SAR	12 b	16	512 KB	80 MHz	64-TQFP Exposed Pad	64-eTQFP (10x10)	Surface Mount	AEC-Q100	FLASH	-40 °C	140 °C
STMicroelectronics SPC570S40E1CEFAY	5.5 V	2.7 V	CANbus LINbus SPI UART/USART	32 K	Automotive	DMA POR WDT	32-Bit Single-Core	External	e200z0h			16	256 KB	80 MHz	64-TQFP Exposed Pad	64-eTQFP (10x10)	Surface Mount	AEC-Q100	FLASH	-40 °C	125 ¯C	12 b
STMicroelectronics SPC570S50E1CEFAY	5.5 V	2.7 V	CANbus LINbus SPI UART/USART	32 K	Automotive	DMA POR WDT	32-Bit Single-Core	External	e200z0h			16	512 KB	80 MHz	64-TQFP Exposed Pad	64-eTQFP (10x10)	Surface Mount	AEC-Q100	FLASH	-40 °C	125 ¯C	12 b
STMicroelectronics SPC570S50E1DEFAR	5.5 V	3 V	CANbus LINbus SPI UART/USART	32 K	Automotive	DMA POR WDT	32-Bit Single-Core	External	e200z0h	SAR	12 b	16	512 KB	80 MHz	64-TQFP Exposed Pad	64-eTQFP (10x10)	Surface Mount	AEC-Q100	FLASH	-40 °C	140 °C
STMicroelectronics SPC570S40E1CEFAR	5.5 V	2.7 V	CANbus LINbus SPI UART/USART	32 K	Automotive	DMA POR WDT	32-Bit Single-Core	External	e200z0h			16	256 KB	80 MHz	64-TQFP Exposed Pad	64-eTQFP (10x10)	Surface Mount	AEC-Q100	FLASH	-40 °C	125 ¯C	12 b

Catalog

32-bit Power Architecture MCU for Automotive Chassis and Safety Applications

Key Features

• High performance e200z0h dual core

- 32-bit Power Architecture technology CPU

- Core frequency as high as 80 MHz

- Single issue 4-stage pipeline in-order execution core

- Variable Length Encoding (VLE)

• Comprehensive new generation ASILD safety concept

- Safety of bus masters (core+INTC, DMA) by delayed lockstep approach

- Safety of storage (Flash, SRAM) by mainly ECC

- Safety of the data path to storage and periphery by mainly End-to-End EDC (E2E EDC)

- Clock and power, generation and distribution, supervised by dedicated monitors

- Fault Collection and Control Unit (FCCU) for collection and reaction to failure notifications

- Memory Error Management Unit (MEMU) for collection and reporting of error events in memories

- Boot time MBIST and LBIST for latent faults

- Check of safety mechanisms availability and error reaction path functionality by dedicated mechanisms

- Safety of the periphery by application-level measures supported by replicated peripheral bridges and by LBIST

- Further measures on dedicated peripherals (e.g. ADC supervisor)

- Junction temperature sensor

- 8-region system memory protection unit (SMPU) with process ID support (tasks isolation)

- Enhanced SW watchdog

- Cyclic redundancy check (CRC) unit

Description

The SPC570Sx is a family of next generation microcontrollers built on the Power Architecture embedded category. The SPC570Sx family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding family of automotive-focused products designed to address the next wave of Chassis and Safety electronics applications within the vehicle. The advanced and cost-efficient host processor core of this automotive controller family complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding) APU, providing improved code density. It operates at speeds of up to 80 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations.