74HCT175 Series

High Speed CMOS Logic Quad D-Type Flip-Flop with Reset

Catalog(4 parts)

Part	Clock Frequency▲▼	Current - Output High, Low▲▼	Package / Case	Package / Case▲▼	Trigger Type	Number of Elements▲▼	Current - Quiescent (Iq)▲▼	Max Propagation Delay @ V, Max CL▲▼	Supplier Device Package	Operating Temperature▲▼	Operating Temperature▲▼	Number of Bits per Element▲▼	Input Capacitance▲▼	Mounting Type	Type	Voltage - Supply▲▼	Voltage - Supply▲▼	Output Type
Texas Instruments CD74HCT175M Flip Flop 1 Element D-Type 4 Bit Positive Edge 16-SOIC (0.154", 3.90mm Width)	25000000 Hz	0.004000000189989805 A, 0.004000000189989805 A	16-SOIC	0.003911599982529879 m, 3.900000095367432 ul	Positive Edge	1 ul	0.000007999999979801942 A	3.2999999177718564e-8 s	16-SOIC	-55 °C	125 °C	4 ul	9.999999960041972e-12 F	Surface Mount	D-Type	5.5 V	4.5 V	Complementary
Texas Instruments CD74HCT175E Flip Flop 1 Element D-Type 4 Bit Positive Edge 16-DIP (0.300", 7.62mm)	25000000 Hz	0.004000000189989805 A, 0.004000000189989805 A	16-DIP	0.007619999814778566 m, 0.007619999814778566 m	Positive Edge	1 ul	0.000007999999979801942 A	3.2999999177718564e-8 s	16-PDIP	-55 °C	125 °C	4 ul	9.999999960041972e-12 F	Through Hole	D-Type	5.5 V	4.5 V	Complementary
Texas Instruments CD74HCT175M96 Flip Flop 1 Element D-Type 4 Bit Positive Edge 16-SOIC (0.154", 3.90mm Width)	25000000 Hz	0.004000000189989805 A, 0.004000000189989805 A	16-SOIC	0.003911599982529879 m, 3.900000095367432 ul	Positive Edge	1 ul	0.000007999999979801942 A	3.2999999177718564e-8 s	16-SOIC	-55 °C	125 °C	4 ul	9.999999960041972e-12 F	Surface Mount	D-Type	5.5 V	4.5 V	Complementary
Texas Instruments CD74HCT175MG4 Flip Flop 1 Element D-Type 4 Bit Positive Edge 16-SOIC (0.154", 3.90mm Width)	25000000 Hz	0.004000000189989805 A, 0.004000000189989805 A	16-SOIC	0.003911599982529879 m, 3.900000095367432 ul	Positive Edge	1 ul	0.000007999999979801942 A	3.2999999177718564e-8 s	16-SOIC	-55 °C	125 °C	4 ul	9.999999960041972e-12 F	Surface Mount	D-Type	5.5 V	4.5 V	Complementary

Key Features

• Common Clock and Asynchronous Reset on Four D-Type Flip-FlopsPositive Edge Pulse TriggeringComplementary OutputsBuffered InputsFanout (Over Temperature Range)Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . -55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOHCommon Clock and Asynchronous Reset on Four D-Type Flip-FlopsPositive Edge Pulse TriggeringComplementary OutputsBuffered InputsFanout (Over Temperature Range)Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . -55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOH

Description

The ’HC175 and ’HCT175 are high speed Quad D-type Flip-Flops with individual D-inputs and Q, Q\ complementary outputs. The devices are fabricated using silicon gate CMOS technology. They have the low power consumption advantage of standard CMOS ICs and the ability to drive 10 LSTTL devices. Information at the D input is transferred to the Q, Q\ outputs on the positive going edge of the clock pulse. All four Flip-Flops are controlled by a common clock (CP) and a common reset (MR\). Resetting is accomplished by a low voltage level independent of the clock. All four Q outputs are reset to a logic 0 and all four Q\ outputs to a logic 1. The ’HC175 and ’HCT175 are high speed Quad D-type Flip-Flops with individual D-inputs and Q, Q\ complementary outputs. The devices are fabricated using silicon gate CMOS technology. They have the low power consumption advantage of standard CMOS ICs and the ability to drive 10 LSTTL devices. Information at the D input is transferred to the Q, Q\ outputs on the positive going edge of the clock pulse. All four Flip-Flops are controlled by a common clock (CP) and a common reset (MR\). Resetting is accomplished by a low voltage level independent of the clock. All four Q outputs are reset to a logic 0 and all four Q\ outputs to a logic 1.