74FCT162501 Series

18-Bit Universal Bus Transceivers with 3-State Outputs

Catalog(6 parts)

Part	Number of Circuits	Package / Case▲▼	Package / Case▲▼	Package / Case	Current - Output High, Low▲▼	Current - Output High, Low▲▼	Mounting Type	Supplier Device Package	Operating Temperature▲▼	Operating Temperature▲▼	Voltage - Supply▲▼	Voltage - Supply▲▼	Package / Case▲▼	Package / Case▲▼
Texas Instruments CY74FCT162501ATPVC Universal Bus Transceiver 18-Bit 56-SSOP	18-Bit	0.007493000011891127 m	0.007499999832361937 m	56-BSSOP	0.024000000208616257 A	0.024000000208616257 A	Surface Mount	56-SSOP	-40 °C	85 °C	5.5 V	4.5 V
Texas Instruments 74FCT162501CTPVCT Universal Bus Transceiver 18-Bit 56-SSOP	18-Bit	0.007493000011891127 m	0.007499999832361937 m	56-BSSOP	0.024000000208616257 A	0.024000000208616257 A	Surface Mount	56-SSOP	-40 °C	85 °C	5.5 V	4.5 V
Texas Instruments 74FCT162501CTPACT Universal Bus Transceiver 18-Bit 56-TSSOP	18-Bit			56-TFSOP	0.024000000208616257 A	0.024000000208616257 A	Surface Mount	56-TSSOP	-40 °C	85 °C	5.5 V	4.5 V	0.006099999882280827 m	0.006095999851822853 m
Texas Instruments 74FCT162501ATPVCT Universal Bus Transceiver 18-Bit 56-SSOP	18-Bit	0.007493000011891127 m	0.007499999832361937 m	56-BSSOP	0.024000000208616257 A	0.024000000208616257 A	Surface Mount	56-SSOP	-40 °C	85 °C	5.5 V	4.5 V
Texas Instruments CY74FCT162501ATPAC
Texas Instruments CY74FCT162501CTPVC Universal Bus Transceiver 18-Bit 56-SSOP	18-Bit	0.007493000011891127 m	0.007499999832361937 m	56-BSSOP	0.024000000208616257 A	0.024000000208616257 A	Surface Mount	56-SSOP	-40 °C	85 °C	5.5 V	4.5 V

Key Features

• Ioffsupports partial-power-down mode operationEdge-rate control circuitry for significantly improved noise characteristicsTypical output skew < 250 psESD > 2000VTSSOP (19.6 mil pitch) and SSOP (25-mil pitch) packagesIndustrial temperature range of -40°C to +85°CVCC= 5V ± 10%CY74FCT16501T Features:64 mA sink current, 32 mA source currentTypical VOLP(ground bounce) <1.0V at VCC= 5V, TA= 25°CCY74FCT162501T Features:Balanced 24 mA output driversReduced system switching noiseTypical VOLP(ground bounce) <0.6V at VCC= 5V, TA= 25°CCY74FCT162H501T Features:Bus hold retains last active stateEliminates the need for external pull-up or pull-down resistorsIoffsupports partial-power-down mode operationEdge-rate control circuitry for significantly improved noise characteristicsTypical output skew < 250 psESD > 2000VTSSOP (19.6 mil pitch) and SSOP (25-mil pitch) packagesIndustrial temperature range of -40°C to +85°CVCC= 5V ± 10%CY74FCT16501T Features:64 mA sink current, 32 mA source currentTypical VOLP(ground bounce) <1.0V at VCC= 5V, TA= 25°CCY74FCT162501T Features:Balanced 24 mA output driversReduced system switching noiseTypical VOLP(ground bounce) <0.6V at VCC= 5V, TA= 25°CCY74FCT162H501T Features:Bus hold retains last active stateEliminates the need for external pull-up or pull-down resistors

Description

These 18-bit universal bus transceivers can be operated in transparent, latched or clock modes by combining D-type latches and D-type flip-flops. Data flow in each direction is controlled by output enable (OEAB and OEBA\), latch enable (LEAB and LEBA), and clock inputs (CLKAB and CLKBA). For A-to-B data flow, the device operates in transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOWlogic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. OEAB performs the output enable function on the B port. Data flow from B-to-A is similar to that of A-to-B and is controlled by OEBA\, LEBA, and CLKBA. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16501T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162501T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162501T is ideal for driving transmission lines. The CY74FCT162H501T is a 24-mA balanced output part, that has "bus hold" on the data inputs. The device retains the input\x92s last state whenever the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs. These 18-bit universal bus transceivers can be operated in transparent, latched or clock modes by combining D-type latches and D-type flip-flops. Data flow in each direction is controlled by output enable (OEAB and OEBA\), latch enable (LEAB and LEBA), and clock inputs (CLKAB and CLKBA). For A-to-B data flow, the device operates in transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOWlogic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. OEAB performs the output enable function on the B port. Data flow from B-to-A is similar to that of A-to-B and is controlled by OEBA\, LEBA, and CLKBA. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16501T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162501T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162501T is ideal for driving transmission lines. The CY74FCT162H501T is a 24-mA balanced output part, that has "bus hold" on the data inputs. The device retains the input\x92s last state whenever the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs.