74LV8151 Series

10-ch, 2-V to 5.5-V buffers with TTL-compatible CMOS inputs

Catalog

10-ch, 2-V to 5.5-V buffers with TTL-compatible CMOS inputs

Part	Package Name	Number of Inputs	Voltage - Supply (Maximum)	Voltage - Supply (Minimum)	Package Length	Package Width	Operating Temperature (Min)	Operating Temperature (Max)	Mounting Type	Logic Type	Schmitt Trigger Input	Output Type	Number of Circuits	Current - Output High	Current - Output Low
Texas Instruments SN74LV8151DGVRE4	24-TFSOP 24-TVSOP	10	5.5 V	2 V	0.173 in	4.4 mm	-40 °C	85 °C	Surface Mount	Buffer/Inverter	No	Single-Ended	1	12 mA	12 mA
Texas Instruments SN74LV8151PWRE4	24-TSSOP	10	5.5 V	2 V	0.173 in	4.4 mm	-40 °C	85 °C	Surface Mount	Buffer/Inverter	No	Single-Ended	1	12 mA	12 mA
Texas Instruments SN74LV8151NTG4	24-DIP 24-PDIP	10	5.5 V	2 V	0.3 in	7.62 mm	-40 °C	85 °C	Through Hole	Buffer/Inverter	No	Single-Ended	1	12 mA	12 mA
Texas Instruments SN74LV8151DWR	24-SOIC	10	5.5 V	2 V	0.295 in	7.5 mm	-40 °C	85 °C	Surface Mount	Buffer/Inverter	No	Single-Ended	1	12 mA	12 mA
Texas Instruments SN74LV8151PWR	24-TSSOP	10	5.5 V	2 V	0.173 in	4.4 mm	-40 °C	85 °C	Surface Mount	Buffer/Inverter	No	Single-Ended	1	12 mA	12 mA
Texas Instruments SN74LV8151PW	24-TSSOP	10	5.5 V	2 V	0.173 in	4.4 mm	-40 °C	85 °C	Surface Mount	Buffer/Inverter	No	Single-Ended	1	12 mA	12 mA
Texas Instruments SN74LV8151NT	24-DIP 24-PDIP	10	5.5 V	2 V	0.3 in	7.62 mm	-40 °C	85 °C	Through Hole	Buffer/Inverter	No	Single-Ended	1	12 mA	12 mA
Texas Instruments SN74LV8151DW	24-SOIC	10	5.5 V	2 V	0.295 in	7.5 mm	-40 °C	85 °C	Surface Mount	Buffer/Inverter	No	Single-Ended	1	12 mA	12 mA
Texas Instruments SN74LV8151DGVR	24-TFSOP 24-TVSOP	10	5.5 V	2 V	0.173 in	4.4 mm	-40 °C	85 °C	Surface Mount	Buffer/Inverter	No	Single-Ended	1	12 mA	12 mA

Catalog

10-ch, 2-V to 5.5-V buffers with TTL-compatible CMOS inputs

Description

The SN74LV8151 is a 10-bit universal Schmitt-trigger buffer with 3-state outputs, designed for 2-V to 5.5-V VCCoperation. The logic control (T/C\) pin allows the user to configure Y1 to Y8 as noninverting or inverting outputs. When T/C\ is high, the Y outputs are noninverted (true logic ), and when T/C\ is low, the Y outputs are inverted (complementary logic). When output-enable (OE)\ input is low, the device passes data from Dn to Yn. When OE\ is high, the Y outputs are in the high-impedance state. The path A to P is a simple Schmitt-trigger buffer, and the path B to N is a simple Schmitt-trigger inverter. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LV8151 is a 10-bit universal Schmitt-trigger buffer with 3-state outputs, designed for 2-V to 5.5-V VCCoperation. The logic control (T/C\) pin allows the user to configure Y1 to Y8 as noninverting or inverting outputs. When T/C\ is high, the Y outputs are noninverted (true logic ), and when T/C\ is low, the Y outputs are inverted (complementary logic). When output-enable (OE)\ input is low, the device passes data from Dn to Yn. When OE\ is high, the Y outputs are in the high-impedance state. The path A to P is a simple Schmitt-trigger buffer, and the path B to N is a simple Schmitt-trigger inverter. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.